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108c98a7d0
In gp10b_ce_nonstall_isr(), we trigger a semaphore wakeup. Currently, we clear the interrupt status register after the wakeup is complete. There is potential for an interrupt to come in while the wake-up operation is in progress, and it is possible that: 1) We miss processing the interrupt in that ISR iteration AND 2) We clear the interrupt status register anyways This change clears the status register before triggering wakeup, so the interrupt will properly re-fire. Bug 200244458 Change-Id: Ia3338252eeea4eb60d11c0e241279989a46dac04 Signed-off-by: Sachit Kadle <skadle@nvidia.com> Reviewed-on: http://git-master/r/1253107 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
83 lines
2.4 KiB
C
83 lines
2.4 KiB
C
/*
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* Pascal GPU series Copy Engine.
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*
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* Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program.
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*/
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#include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */
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#include "hw_ce_gp10b.h"
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#include "ce_gp10b.h"
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static void ce_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr)
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{
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gk20a_dbg(gpu_dbg_intr, "ce non-blocking pipe interrupt\n");
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/* wake theads waiting in this channel */
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gk20a_channel_semaphore_wakeup(g, true);
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return;
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}
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static u32 ce_blockpipe_isr(struct gk20a *g, u32 fifo_intr)
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{
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gk20a_dbg(gpu_dbg_intr, "ce blocking pipe interrupt\n");
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return ce_intr_status_blockpipe_pending_f();
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}
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static u32 ce_launcherr_isr(struct gk20a *g, u32 fifo_intr)
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{
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gk20a_dbg(gpu_dbg_intr, "ce launch error interrupt\n");
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return ce_intr_status_launcherr_pending_f();
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}
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static void gp10b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
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{
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u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id));
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u32 clear_intr = 0;
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gk20a_dbg(gpu_dbg_intr, "ce isr %08x %08x\n", ce_intr, inst_id);
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/* clear blocking interrupts: they exibit broken behavior */
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if (ce_intr & ce_intr_status_blockpipe_pending_f())
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clear_intr |= ce_blockpipe_isr(g, ce_intr);
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if (ce_intr & ce_intr_status_launcherr_pending_f())
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clear_intr |= ce_launcherr_isr(g, ce_intr);
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gk20a_writel(g, ce_intr_status_r(inst_id), clear_intr);
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return;
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}
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static void gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
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{
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u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id));
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gk20a_dbg(gpu_dbg_intr, "ce nonstall isr %08x %08x\n", ce_intr, inst_id);
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if (ce_intr & ce_intr_status_nonblockpipe_pending_f()) {
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gk20a_writel(g, ce_intr_status_r(inst_id),
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ce_intr_status_nonblockpipe_pending_f());
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ce_nonblockpipe_isr(g, ce_intr);
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}
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return;
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}
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void gp10b_init_ce(struct gpu_ops *gops)
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{
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gops->ce2.isr_stall = gp10b_ce_isr;
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gops->ce2.isr_nonstall = gp10b_ce_nonstall_isr;
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}
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