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dacdaf0778
nvgpu_channel_get_max_subctx_count() right now always returns max subctx count for 0th instance. Update this function to return max subctx count for GPU instance for which channel is allocated. For CE channels that are allocated and managed by nvgpu, cdev pointer is not set in channel private data (since it is assigned in OS specific code). For those channels continue returning max subctx count for 0th instance. CE channels should not need subcontexts anyways. Add nvgpu_cdev pointer in struct nvgpu_channel_linux. Assign it in __gk20a_channel_open() and clear it in gk20a_channel_release() Move code to get runlist and gpu_instance_id after nvgpu_get() call. Accesses to gk20a pointer should always come after nvgpu_get(). Also add a debug print to dump runlist_id and gpu_instance_id being used for channel. Jira NVGPU-5648 Change-Id: Idf58ccefdb7dc9fec78100f79c647e5a00b8fb29 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2438924 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Lakshmanan M <lm@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
112 lines
3.0 KiB
C
112 lines
3.0 KiB
C
/*
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef NVGPU_LINUX_CHANNEL_H
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#define NVGPU_LINUX_CHANNEL_H
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#include <linux/workqueue.h>
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#include <linux/dma-buf.h>
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#include <nvgpu/types.h>
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struct nvgpu_channel;
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struct nvgpu_gpfifo;
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struct nvgpu_submit_gpfifo_args;
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struct nvgpu_channel_fence;
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struct nvgpu_fence_type;
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struct nvgpu_swprofile;
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struct nvgpu_os_linux;
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struct nvgpu_cdev;
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struct sync_fence;
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struct sync_timeline;
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struct nvgpu_channel_completion_cb {
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/*
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* Signal channel owner via a callback, if set, in job cleanup with
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* schedule_work. Means that something finished on the channel (perhaps
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* more than one job).
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*/
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void (*fn)(struct nvgpu_channel *, void *);
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void *user_data;
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/* Make access to the two above atomic */
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struct nvgpu_spinlock lock;
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/* Per-channel async work task, cannot reschedule itself */
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struct work_struct work;
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};
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struct nvgpu_error_notifier {
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struct dma_buf *dmabuf;
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void *vaddr;
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struct nvgpu_notification *notification;
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struct nvgpu_mutex mutex;
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};
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/*
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* channel-global data for sync fences created from the hardware
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* synchronization primitive in each particular channel.
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*/
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struct nvgpu_os_fence_framework {
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#if defined(CONFIG_NVGPU_SYNCFD_ANDROID)
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struct sync_timeline *timeline;
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#elif defined(CONFIG_NVGPU_SYNCFD_STABLE)
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u64 context;
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bool exists;
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#endif
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};
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struct nvgpu_usermode_bufs_linux {
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/*
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* Common low level info of these is stored in nvgpu_mems in
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* channel_gk20a; these hold lifetimes for the actual dmabuf and its
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* dma mapping.
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*/
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struct nvgpu_usermode_buf_linux {
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struct dma_buf *dmabuf;
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struct dma_buf_attachment *attachment;
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struct sg_table *sgt;
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} gpfifo, userd;
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};
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struct nvgpu_channel_linux {
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struct nvgpu_channel *ch;
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struct nvgpu_os_fence_framework fence_framework;
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struct nvgpu_channel_completion_cb completion_cb;
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struct nvgpu_error_notifier error_notifier;
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struct dma_buf *cyclestate_buffer_handler;
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struct nvgpu_usermode_bufs_linux usermode;
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struct nvgpu_cdev *cdev;
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};
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u32 nvgpu_submit_gpfifo_user_flags_to_common_flags(u32 user_flags);
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int nvgpu_channel_init_support_linux(struct nvgpu_os_linux *l);
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void nvgpu_channel_remove_support_linux(struct nvgpu_os_linux *l);
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/* Deprecated. Use fences in new code. */
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struct nvgpu_channel *gk20a_open_new_channel_with_cb(struct gk20a *g,
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void (*update_fn)(struct nvgpu_channel *, void *),
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void *update_fn_data,
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u32 runlist_id,
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bool is_privileged_channel);
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#endif
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