Mahantesh Kumbar ce7d589a4d gpu: nvgpu: ga10b: add PMU interrupt check hal ...

-GA10B PMU IRQ registers are not accessible when NVRISCV PRIV lockdown
 is engaged, so need to skip accessing IRQ registers.

NVGPU-7061

Change-Id: If5233e502a9bef838839376c412582e08d729a99
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2636964
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>

2021-12-06 04:37:39 -08:00

..

nvgpu

gpu: nvgpu: ga10b: add PMU interrupt check hal

2021-12-06 04:37:39 -08:00

Makefile

gpu: nvgpu: move linux configs from Kconfig file

2020-12-15 14:13:28 -06:00