seshendra Gadagottu cedb24c7a0 gpu: nvgpu: gv11b: correct wl reg offset ...

Corrected whitelist register address offset for
gr_pri_gpcs_tpcs_sm_disp_ctrl. This offset value is
changed for gv11b from gp10b. With wrong offset value,
gl tests are generating "unhandled fecs error interrupt
0x00000002 for channel xxx".

Bug 1958308

Change-Id: Iabfbb20ea1ee4ca8567d0cda940fa1e8cbff1bac
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1562615
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit

2017-09-19 17:45:27 -07:00

..

gpu/nvgpu

gpu: nvgpu: gv11b: correct wl reg offset

2017-09-19 17:45:27 -07:00