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git://nv-tegra.nvidia.com/linux-nvgpu.git
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cfa360f5b8
Add new API nvgpu_grmgr_get_num_gr_instances() that returns number of GR instance enumerated by GR manager. This just returns number of sys pipes enabled since it is same as number of GR instances. For consistency until common.gr supports multiple GR instances completely, add a temporary macro NVGPU_GR_NUM_INSTANCES and set it to 1. If this macro is changed to 0 (for local MIG testing), fall back to use nvgpu_grmgr_get_num_gr_instances() to get enumerated number of GR instances. Use a for loop to initialize other variables of struct nvgpu_gr. Remove unnecessary NULL check in nvgpu_gr_alloc() since struct gk20a pointer can never be NULL in this path. Also remove corresponding unit test code. Jira NVGPU-5648 Change-Id: Id151d634a23235381229044f2a9af89e390886f2 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2400151 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
118 lines
2.9 KiB
C
118 lines
2.9 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/types.h>
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#include <nvgpu/gr/gr_utils.h>
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#include <nvgpu/gr/config.h>
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#include "gr_priv.h"
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u32 nvgpu_gr_checksum_u32(u32 a, u32 b)
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{
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return nvgpu_safe_cast_u64_to_u32(((u64)a + (u64)b) & (U32_MAX));
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}
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struct nvgpu_gr_falcon *nvgpu_gr_get_falcon_ptr(struct gk20a *g)
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{
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return g->gr->falcon;
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}
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struct nvgpu_gr_config *nvgpu_gr_get_config_ptr(struct gk20a *g)
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{
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return g->gr->config;
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}
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struct nvgpu_gr_intr *nvgpu_gr_get_intr_ptr(struct gk20a *g)
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{
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return g->gr->intr;
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}
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#ifdef CONFIG_NVGPU_NON_FUSA
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u32 nvgpu_gr_get_override_ecc_val(struct gk20a *g)
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{
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return g->gr->fecs_feature_override_ecc_val;
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}
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void nvgpu_gr_override_ecc_val(struct nvgpu_gr *gr, u32 ecc_val)
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{
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gr->fecs_feature_override_ecc_val = ecc_val;
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}
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#endif
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#ifdef CONFIG_NVGPU_GRAPHICS
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struct nvgpu_gr_zcull *nvgpu_gr_get_zcull_ptr(struct gk20a *g)
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{
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return g->gr->zcull;
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}
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struct nvgpu_gr_zbc *nvgpu_gr_get_zbc_ptr(struct gk20a *g)
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{
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return g->gr->zbc;
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}
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#endif
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#ifdef CONFIG_NVGPU_FECS_TRACE
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struct nvgpu_gr_global_ctx_buffer_desc *nvgpu_gr_get_global_ctx_buffer_ptr(
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struct gk20a *g)
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{
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return g->gr->global_ctx_buffer;
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}
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#endif
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#ifdef CONFIG_NVGPU_CILP
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u32 nvgpu_gr_get_cilp_preempt_pending_chid(struct gk20a *g)
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{
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return g->gr->cilp_preempt_pending_chid;
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}
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void nvgpu_gr_clear_cilp_preempt_pending_chid(struct gk20a *g)
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{
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g->gr->cilp_preempt_pending_chid =
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NVGPU_INVALID_CHANNEL_ID;
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}
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#endif
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#ifdef CONFIG_NVGPU_DEBUGGER
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struct nvgpu_gr_obj_ctx_golden_image *nvgpu_gr_get_golden_image_ptr(
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struct gk20a *g)
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{
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return g->gr->golden_image;
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}
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struct nvgpu_gr_hwpm_map *nvgpu_gr_get_hwpm_map_ptr(struct gk20a *g)
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{
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return g->gr->hwpm_map;
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}
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void nvgpu_gr_reset_falcon_ptr(struct gk20a *g)
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{
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g->gr->falcon = NULL;
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}
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void nvgpu_gr_reset_golden_image_ptr(struct gk20a *g)
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{
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g->gr->golden_image = NULL;
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}
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#endif
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