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3fb2a2e209
On successful obj_ctx allocation, set ctx_initialized member in gr_ctx to true and when it is true then only invoke free_gr_ctx. With this we can get rid of tsg->vm check while calling free_gr_ctx. tsg->vm will go away with multiple address spaces support in TSG. Bug 3677982 Change-Id: I4a64842411ce4ab157010808e4e8e4d5cd254a7f Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2746803 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: Scott Long <scottl@nvidia.com> Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com> GVS: Gerrit_Virtual_Submit
166 lines
3.8 KiB
C
166 lines
3.8 KiB
C
/*
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* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GR_CTX_PRIV_H
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#define NVGPU_GR_CTX_PRIV_H
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struct nvgpu_mem;
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/**
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* Patch context buffer descriptor structure.
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*
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* Pointer to this structure is maintained in #nvgpu_gr_ctx structure.
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*/
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struct patch_desc {
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/**
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* Count of entries written into patch context buffer.
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*/
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u32 data_count;
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};
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#ifdef CONFIG_NVGPU_GRAPHICS
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struct zcull_ctx_desc {
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u64 gpu_va;
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u32 ctx_sw_mode;
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};
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#endif
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#ifdef CONFIG_NVGPU_DEBUGGER
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struct pm_ctx_desc {
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u32 pm_mode;
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bool mapped;
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};
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#endif
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/**
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* GR context descriptor structure.
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*
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* This structure stores various properties of all GR context buffers.
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*/
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struct nvgpu_gr_ctx_desc {
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/**
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* Array to store all GR context buffer sizes.
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*/
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u32 size[NVGPU_GR_CTX_COUNT];
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#ifdef CONFIG_NVGPU_GRAPHICS
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bool force_preemption_gfxp;
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#endif
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#ifdef CONFIG_NVGPU_CILP
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bool force_preemption_cilp;
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#endif
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#ifdef CONFIG_DEBUG_FS
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bool dump_ctxsw_stats_on_channel_close;
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#endif
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};
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/**
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* Graphics context buffer structure.
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*
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* This structure stores all the properties of a graphics context
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* buffer. One graphics context is allocated per GPU Time Slice
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* Group (TSG).
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*/
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struct nvgpu_gr_ctx {
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/**
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* Context ID read from graphics context buffer.
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*/
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u32 ctx_id;
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/**
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* Flag to indicate if above context ID is valid or not.
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*/
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bool ctx_id_valid;
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/**
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* Array to store all GR context buffers.
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*/
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struct nvgpu_mem mem[NVGPU_GR_CTX_COUNT];
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/**
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* Cacheability flags for mapping the context buffers.
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*/
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u32 mapping_flags[NVGPU_GR_CTX_COUNT];
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/**
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* Pointer to structure that holds GPU mapping of context buffers.
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* These mappings will exist for the lifetime of TSG when the
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* subcontexts are not enabled.
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*/
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struct nvgpu_gr_ctx_mappings *mappings;
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/**
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* Patch context buffer descriptor struct.
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*/
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struct patch_desc patch_ctx;
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#ifdef CONFIG_NVGPU_GRAPHICS
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struct zcull_ctx_desc zcull_ctx;
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#endif
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#ifdef CONFIG_NVGPU_DEBUGGER
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struct pm_ctx_desc pm_ctx;
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#endif
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/**
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* Graphics preemption mode of the graphics context.
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*/
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u32 graphics_preempt_mode;
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/**
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* Compute preemption mode of the graphics context.
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*/
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u32 compute_preempt_mode;
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#ifdef CONFIG_NVGPU_NON_FUSA
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bool golden_img_loaded;
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#endif
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#ifdef CONFIG_NVGPU_CILP
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bool cilp_preempt_pending;
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#endif
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#ifdef CONFIG_NVGPU_DEBUGGER
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bool boosted_ctx;
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#endif
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/**
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* TSG identifier corresponding to the graphics context.
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*/
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u32 tsgid;
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bool ctx_initialized;
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#ifdef CONFIG_NVGPU_SM_DIVERSITY
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/** SM diversity configuration offset.
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* It is valid only if NVGPU_SUPPORT_SM_DIVERSITY support is true.
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* else input param is just ignored.
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* A valid offset starts from 0 to
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* (#gk20a.max_sm_diversity_config_count - 1).
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*/
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u32 sm_diversity_config;
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#endif
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};
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#endif /* NVGPU_GR_CTX_PRIV_H */
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