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2b2beb7fb6
Below commit replaced ga10b_ptimer_isr with gk20a_ptimer_isr.
commit 1528170f1c ("gpu: nvgpu: ga10b: update pri_hub and
ptimer error handling")
However, ga10b needs separate hal as timer_pri_timeout_save_0_addr_v()
definition is different for ga10b.
JIRA NVGPU-7986
Change-Id: I9593c90a41c5abdcad2989eb0867b921288064af
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2676699
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
70 lines
2.3 KiB
C
70 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/log.h>
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/nvgpu_err.h>
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#include "ptimer_ga10b.h"
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#include <nvgpu/hw/ga10b/hw_timer_ga10b.h>
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void ga10b_ptimer_isr(struct gk20a *g)
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{
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u32 save0, save1, fecs_errcode = 0;
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u32 error_addr;
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save0 = nvgpu_readl(g, timer_pri_timeout_save_0_r());
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if (timer_pri_timeout_save_0_fecs_tgt_v(save0) != 0U) {
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/*
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* write & addr fields in timeout_save0
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* might not be reliable
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*/
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fecs_errcode = nvgpu_readl(g,
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timer_pri_timeout_fecs_errcode_r());
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}
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save1 = nvgpu_readl(g, timer_pri_timeout_save_1_r());
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error_addr = timer_pri_timeout_save_0_addr_v(save0) << 2;
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nvgpu_err(g, "PRI timeout: ADR 0x%08x "
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"%s DATA 0x%08x",
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error_addr,
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(timer_pri_timeout_save_0_write_v(save0) != 0U) ?
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"WRITE" : "READ", save1);
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nvgpu_writel(g, timer_pri_timeout_save_0_r(), 0);
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nvgpu_writel(g, timer_pri_timeout_save_1_r(), 0);
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if (fecs_errcode != 0U) {
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nvgpu_err(g, "FECS_ERRCODE 0x%08x", fecs_errcode);
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if (g->ops.priv_ring.decode_error_code != NULL) {
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g->ops.priv_ring.decode_error_code(g,
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fecs_errcode);
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}
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}
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nvgpu_report_err_to_sdl(g, NVGPU_ERR_MODULE_PRI,
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GPU_PRI_TIMEOUT_ERROR);
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}
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