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git://nv-tegra.nvidia.com/linux-nvgpu.git
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74ae8bb20b
dma_buf private data is not supported in upstream kernel. Update the logic of pin/unpin when this support is not present. Separate out the related functions to new file and select logic based on new config flag CONFIG_NVGPU_DMABUF_HAS_DRVDATA. Bug 2834141 Change-Id: I921758727b1bfc3690f2ab26bccd9befae14d782 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2294098 Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
100 lines
2.5 KiB
C
100 lines
2.5 KiB
C
/*
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef NVGPU_DMABUF_PRIV_H
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#define NVGPU_DMABUF_PRIV_H
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#ifdef CONFIG_NVGPU_DMABUF_HAS_DRVDATA
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#include <nvgpu/comptags.h>
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#include <nvgpu/list.h>
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#include <nvgpu/lock.h>
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#include <nvgpu/gmmu.h>
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struct sg_table;
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struct dma_buf;
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struct dma_buf_attachment;
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struct device;
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struct gk20a;
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struct gk20a_buffer_state {
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struct nvgpu_list_node list;
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/* The valid compbits and the fence must be changed atomically. */
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struct nvgpu_mutex lock;
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/*
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* Offset of the surface within the dma-buf whose state is
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* described by this struct (one dma-buf can contain multiple
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* surfaces with different states).
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*/
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size_t offset;
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/* A bitmask of valid sets of compbits (0 = uncompressed). */
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u32 valid_compbits;
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/* The ZBC color used on this buffer. */
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u32 zbc_color;
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/*
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* This struct reflects the state of the buffer when this
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* fence signals.
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*/
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struct nvgpu_fence_type *fence;
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};
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static inline struct gk20a_buffer_state *
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gk20a_buffer_state_from_list(struct nvgpu_list_node *node)
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{
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return (struct gk20a_buffer_state *)
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((uintptr_t)node - offsetof(struct gk20a_buffer_state, list));
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};
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struct gk20a_dmabuf_priv {
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struct nvgpu_mutex lock;
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struct gk20a *g;
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struct gk20a_comptag_allocator *comptag_allocator;
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struct gk20a_comptags comptags;
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struct dma_buf_attachment *attach;
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struct sg_table *sgt;
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int pin_count;
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struct nvgpu_list_node states;
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u64 buffer_id;
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};
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struct sg_table *gk20a_mm_pin_has_drvdata(struct device *dev,
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struct dma_buf *dmabuf,
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struct dma_buf_attachment **attachment);
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void gk20a_mm_unpin_has_drvdata(struct device *dev,
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struct dma_buf *dmabuf,
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struct dma_buf_attachment *attachment,
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struct sg_table *sgt);
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int gk20a_dmabuf_alloc_drvdata(struct dma_buf *dmabuf, struct device *dev);
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int gk20a_dmabuf_get_state(struct dma_buf *dmabuf, struct gk20a *g,
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u64 offset, struct gk20a_buffer_state **state);
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#endif
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#endif
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