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44b9d5fdb0
Used GPU device name in clock get operation (instead of fixed name), to make operation is common for GK20A and GM20B. Updated clock ids in tegra clock framework accordingly. Bug 1450787 Change-Id: Ifd5b9c3a6fd8db5b06e6dcd989285e8410794803 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/441711 Reviewed-by: Bo Yan <byan@nvidia.com> Tested-by: Bo Yan <byan@nvidia.com>
83 lines
2.1 KiB
C
83 lines
2.1 KiB
C
/*
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* drivers/video/tegra/host/gk20a/clk_gk20a.h
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*
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* GK20A Graphics
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*
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* Copyright (c) 2011 - 2014, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef _NVHOST_CLK_GK20A_H_
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#define _NVHOST_CLK_GK20A_H_
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#include <linux/mutex.h>
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#define GPUFREQ_TABLE_END ~(u32)1
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enum {
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/* only one PLL for gk20a */
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GK20A_GPC_PLL = 0,
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};
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struct pll {
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u32 id;
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u32 clk_in; /* KHz */
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u32 M;
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u32 N;
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u32 PL;
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u32 freq; /* KHz */
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bool enabled;
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};
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struct pll_parms {
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u32 min_freq, max_freq; /* KHz */
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u32 min_vco, max_vco; /* KHz */
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u32 min_u, max_u; /* KHz */
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u32 min_M, max_M;
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u32 min_N, max_N;
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u32 min_PL, max_PL;
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};
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struct clk_gk20a {
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struct gk20a *g;
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struct clk *tegra_clk;
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struct pll gpc_pll;
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u32 pll_delay; /* default PLL settle time */
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struct mutex clk_mutex;
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bool sw_ready;
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bool clk_hw_on;
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bool debugfs_set;
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};
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/* APIs used for both GK20A and GM20B */
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unsigned long gk20a_clk_get_rate(struct gk20a *g);
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int gk20a_clk_set_rate(struct gk20a *g, unsigned long rate);
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long gk20a_clk_round_rate(struct gk20a *g, unsigned long rate);
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struct clk *gk20a_clk_get(struct gk20a *g);
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#define KHZ 1000
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#define MHZ 1000000
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static inline unsigned long rate_gpc2clk_to_gpu(unsigned long rate)
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{
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/* convert the kHz gpc2clk frequency to Hz gpcpll frequency */
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return (rate * KHZ) / 2;
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}
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static inline unsigned long rate_gpu_to_gpc2clk(unsigned long rate)
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{
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/* convert the Hz gpcpll frequency to kHz gpc2clk frequency */
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return (rate * 2) / KHZ;
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}
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#endif /* _NVHOST_CLK_GK20A_H_ */
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