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b80b2bdab8
a. LAUNCH_ERR
- Userspace error.
- Triggered due to faulty launch.
- Handle using recovery to reset CE engine and teardown the
faulty channel.
b. An INVALID_CONFIG -
- Triggered when LCE is mapped to floorswept PCE.
- On iGPU, we use the default PCE 2 LCE HW mapping.
The default mapping can be read from NV_CE_PCE2LCE_CONFIG
INIT value in CE refmanual.
- NvGPU driver configures the mapping on dGPUs (currently only on
Turing).
- So, this interrupt can only be triggered if there is
kernel or HW error
- Recovery ( which is killing the context + engine reset) will
not help resolve this error.
- Trigger Quiesce as part of handling.
c. A MTHD_BUFFER_FAULT -
- NvGPU driver allocates fault buffers for all TSGs or contexts,
maps them in BAR2 VA space and writes the VA into channel
instance block.
- Can be triggered only due to kernel bug
- Recovery will not help, need quiesce
d. FBUF_CRC_FAIL
- Triggered when the CRC entry read from the method fault buffer
does not match the computed CRC from the methods contained in
the buffer.
- This indicates memory corruption and is a fatal interrupt which
at least requires the LCE to be reset before operations can
start again, if not the entire GPU.
- Better to quiesce on memory corruption
CE Engine reset (via recovery) will not help.
e. FBUF_MAGIC_CHK_FAIL
- Triggered when the MAGIC_NUM entry read from the method fault
buf does not match NV_CE_MTHD_BUFFER_GLOBAL_HDR_MAGIC_NUM_VAL
- This indicates memory corruption and is a fatal interrupt
- Better to quiesce on memory corruption
f. STALLING_DEBUG
- Only triggered with SW write for debug purposes
- Debug interrupt, currently ignored
Move launch error handling from GP10b to GV11b HAL as -
1. LAUNCHERR_REPORT errcode METHOD_BUFFER_ACCESS_FAULT is not
defined on Pascal
2. We do not support GP10b on dev-main ToT
JIRA NVGPU-8102
Change-Id: Idc84119bc23b5e85f3479fe62cc8720e98b627a5
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2678893
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
109 lines
3.2 KiB
C
109 lines
3.2 KiB
C
/*
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* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/types.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/engines.h>
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#include <nvgpu/device.h>
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#include <nvgpu/ce.h>
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#include <nvgpu/power_features/cg.h>
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#include <nvgpu/cic_mon.h>
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#include <nvgpu/mc.h>
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#include <nvgpu/rc.h>
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#include <nvgpu/nvgpu_init.h>
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int nvgpu_ce_init_support(struct gk20a *g)
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{
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int err = 0;
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if (g->ops.ce.set_pce2lce_mapping != NULL) {
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g->ops.ce.set_pce2lce_mapping(g);
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}
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/*
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* Bug 1895019
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* Each time PCE2LCE config is updated and if it happens to
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* map a LCE which was previously unmapped, then ELCG would have turned
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* off the clock to the unmapped LCE and when the LCE config is updated,
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* a race occurs between the config update and ELCG turning on the clock
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* to that LCE, this might result in LCE dropping the config update.
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* To avoid such a race, each time PCE2LCE config is updated toggle
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* resets for all LCEs.
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*/
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err = nvgpu_mc_reset_devtype(g, NVGPU_DEVTYPE_LCE);
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if (err != 0) {
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nvgpu_err(g, "NVGPU_DEVTYPE_LCE reset failed");
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return err;
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}
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nvgpu_cg_slcg_ce2_load_enable(g);
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nvgpu_cg_blcg_ce_load_enable(g);
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#if defined(CONFIG_NVGPU_NON_FUSA)
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nvgpu_cg_elcg_ce_load_enable(g);
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#endif
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if (g->ops.ce.init_prod_values != NULL) {
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g->ops.ce.init_prod_values(g);
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}
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#ifdef CONFIG_NVGPU_NONSTALL_INTR
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if (g->ops.ce.init_hw != NULL) {
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g->ops.ce.init_hw(g);
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}
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#endif
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if (g->ops.ce.intr_enable != NULL) {
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g->ops.ce.intr_enable(g, true);
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}
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/** Enable interrupts at MC level */
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nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_CE, NVGPU_CIC_INTR_ENABLE);
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#ifdef CONFIG_NVGPU_NONSTALL_INTR
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nvgpu_cic_mon_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_CE, NVGPU_CIC_INTR_ENABLE);
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#endif
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return 0;
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}
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void nvgpu_ce_stall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
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{
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bool needs_rc = false;
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bool needs_quiesce = false;
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if (g->ops.ce.isr_stall != NULL) {
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g->ops.ce.isr_stall(g, inst_id, pri_base, &needs_rc,
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&needs_quiesce);
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}
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if (needs_quiesce) {
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nvgpu_sw_quiesce(g);
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}
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if (needs_rc) {
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nvgpu_log(g, gpu_dbg_intr,
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"Recovery needed to handle CE interrupt.");
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nvgpu_rc_ce_fault(g, inst_id);
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}
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}
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