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36da08388b
nvgpu_pbdma_init_intr_descs was checking device_fatal_0_intr_descs instead of channel_fatal_0_intr_descs to assign f->intr.pbdma.channel_fatal_0. Jira NVGPU-3490 Change-Id: Ied8fb9db0bd43e7cb76b6b9f41b0ed5639181d72 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2241798 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
91 lines
2.7 KiB
C
91 lines
2.7 KiB
C
/*
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* Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/pbdma.h>
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bool nvgpu_pbdma_find_for_runlist(struct gk20a *g,
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u32 runlist_id, u32 *pbdma_id)
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{
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struct nvgpu_fifo *f = &g->fifo;
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bool found_pbdma_for_runlist = false;
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u32 runlist_bit;
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u32 id = U32_MAX;
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runlist_bit = BIT32(runlist_id);
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for (id = 0U; id < f->num_pbdma; id++) {
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if ((f->pbdma_map[id] & runlist_bit) != 0U) {
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nvgpu_log_info(g, "gr info: pbdma_map[%d]=%d",
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id, f->pbdma_map[id]);
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found_pbdma_for_runlist = true;
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break;
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}
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}
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*pbdma_id = id;
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return found_pbdma_for_runlist;
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}
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static void nvgpu_pbdma_init_intr_descs(struct gk20a *g)
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{
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struct nvgpu_fifo *f = &g->fifo;
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if (g->ops.pbdma.device_fatal_0_intr_descs != NULL) {
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f->intr.pbdma.device_fatal_0 =
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g->ops.pbdma.device_fatal_0_intr_descs();
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}
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if (g->ops.pbdma.channel_fatal_0_intr_descs != NULL) {
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f->intr.pbdma.channel_fatal_0 =
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g->ops.pbdma.channel_fatal_0_intr_descs();
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}
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if (g->ops.pbdma.restartable_0_intr_descs != NULL) {
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f->intr.pbdma.restartable_0 =
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g->ops.pbdma.restartable_0_intr_descs();
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}
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}
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int nvgpu_pbdma_setup_sw(struct gk20a *g)
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{
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struct nvgpu_fifo *f = &g->fifo;
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f->num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA);
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f->pbdma_map = nvgpu_kzalloc(g, f->num_pbdma * sizeof(*f->pbdma_map));
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if (f->pbdma_map == NULL) {
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return -ENOMEM;
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}
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g->ops.fifo.init_pbdma_map(g, f->pbdma_map, f->num_pbdma);
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nvgpu_pbdma_init_intr_descs(g);
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return 0;
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}
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void nvgpu_pbdma_cleanup_sw(struct gk20a *g)
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{
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struct nvgpu_fifo *f = &g->fifo;
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nvgpu_kfree(g, f->pbdma_map);
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f->pbdma_map = NULL;
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}
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