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7d3ae08847
Move fifo related code to common/vgpu/fifo and create new child units fifo, channel, tsg, preempt, engines. Also update arch YAML to include newly created files related to fifo unit. Jira GVSCI-994 Change-Id: I79897df4e729e0506702832ba62c1694c3f42280 Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2138388 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Nirav Patel <nipatel@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
85 lines
2.4 KiB
C
85 lines
2.4 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/atomic.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/channel.h>
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#include <nvgpu/fifo.h>
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#include <nvgpu/tsg.h>
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#include <nvgpu/preempt.h>
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#include <nvgpu/vgpu/vgpu_ivc.h>
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#include <nvgpu/vgpu/vgpu.h>
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#include "preempt_vgpu.h"
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#include "common/vgpu/ivc/comm_vgpu.h"
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int vgpu_fifo_preempt_channel(struct gk20a *g, struct nvgpu_channel *ch)
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{
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struct tegra_vgpu_cmd_msg msg;
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struct tegra_vgpu_channel_config_params *p =
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&msg.params.channel_config;
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int err;
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nvgpu_log_fn(g, " ");
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if (!nvgpu_atomic_read(&ch->bound)) {
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return 0;
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}
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msg.cmd = TEGRA_VGPU_CMD_CHANNEL_PREEMPT;
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msg.handle = vgpu_get_handle(g);
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p->handle = ch->virt_ctx;
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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if (err || msg.ret) {
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nvgpu_err(g,
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"preempt channel %d failed", ch->chid);
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err = -ENOMEM;
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}
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return err;
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}
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int vgpu_fifo_preempt_tsg(struct gk20a *g, struct nvgpu_tsg *tsg)
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{
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struct tegra_vgpu_cmd_msg msg;
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struct tegra_vgpu_tsg_preempt_params *p =
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&msg.params.tsg_preempt;
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int err;
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nvgpu_log_fn(g, " ");
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msg.cmd = TEGRA_VGPU_CMD_TSG_PREEMPT;
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msg.handle = vgpu_get_handle(g);
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p->tsg_id = tsg->tsgid;
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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err = err ? err : msg.ret;
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if (err) {
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nvgpu_err(g,
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"preempt tsg %u failed", tsg->tsgid);
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}
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return err;
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}
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