mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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1e95ebef53
Golden image creation asks FECS to bind inst_block directly. It does not need any setup on esched. Separating it from tsg/ch makes it for flexible. Jira GVSCI-15771 Change-Id: Id446371eb60b9520a7a284120a72c13d2215f4ea Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2854096 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Sagar Kamble <skamble@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
81 lines
2.7 KiB
C
81 lines
2.7 KiB
C
/*
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* Copyright (c) 2022-2023, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GR_CTX_MAPPINGS_PRIV_H
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#define NVGPU_GR_CTX_MAPPINGS_PRIV_H
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#include <nvgpu/types.h>
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struct nvgpu_tsg;
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struct vm_gk20a;
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struct nvgpu_gr_ctx_mappings {
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/** TSG whose gr ctx mappings are tracked in this object */
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struct nvgpu_tsg *tsg;
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/** GPU virtual address space to which gr ctx buffers are mapped */
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struct vm_gk20a *vm;
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/**
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* Array to store GPU virtual addresses of all TSG context
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* buffers.
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*/
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u64 ctx_buffer_va[NVGPU_GR_CTX_COUNT];
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/**
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* Array to store GPU virtual addresses of all global context
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* buffers.
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*/
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u64 global_ctx_buffer_va[NVGPU_GR_GLOBAL_CTX_VA_COUNT];
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/**
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* Array to store indexes of global context buffers
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* corresponding to GPU virtual addresses above.
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*/
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u32 global_ctx_buffer_index[NVGPU_GR_GLOBAL_CTX_VA_COUNT];
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/**
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* GR ctx mappings' entry in TSG's (#nvgpu_tsg) mappings list
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* #gr_ctx_mappings_list.
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*/
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struct nvgpu_list_node tsg_entry;
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/**
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* List of GR subcontexts (#nvgpu_gr_subctx) using this mapping.
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*/
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struct nvgpu_list_node subctx_list;
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};
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int nvgpu_gr_ctx_mappings_map_global_ctx_buffers(struct gk20a *g,
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struct nvgpu_gr_global_ctx_buffer_desc *global_ctx_buffer,
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bool support_gfx,
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struct nvgpu_gr_ctx_mappings *mappings,
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bool vpr);
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void nvgpu_gr_ctx_mappings_unmap_global_ctx_buffers(
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struct nvgpu_gr_global_ctx_buffer_desc *global_ctx_buffer,
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struct nvgpu_gr_ctx_mappings *mappings);
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void nvgpu_gr_ctx_mappings_unmap_ctx_buffer(struct nvgpu_gr_ctx *ctx,
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u32 index, struct nvgpu_gr_ctx_mappings *mappings);
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#endif /* NVGPU_GR_CTX_MAPPINGS_PRIV_H */
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