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7d3ae08847
Move fifo related code to common/vgpu/fifo and create new child units fifo, channel, tsg, preempt, engines. Also update arch YAML to include newly created files related to fifo unit. Jira GVSCI-994 Change-Id: I79897df4e729e0506702832ba62c1694c3f42280 Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2138388 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Nirav Patel <nipatel@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
49 lines
2.0 KiB
C
49 lines
2.0 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_TSG_VGPU_H
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#define NVGPU_TSG_VGPU_H
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#include <nvgpu/types.h>
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struct gk20a;
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struct nvgpu_channel;
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struct nvgpu_tsg;
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int vgpu_tsg_open(struct nvgpu_tsg *tsg);
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void vgpu_tsg_release(struct nvgpu_tsg *tsg);
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void vgpu_tsg_enable(struct nvgpu_tsg *tsg);
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int vgpu_tsg_bind_channel(struct nvgpu_tsg *tsg, struct nvgpu_channel *ch);
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int vgpu_tsg_unbind_channel(struct nvgpu_tsg *tsg, struct nvgpu_channel *ch);
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int vgpu_tsg_set_timeslice(struct nvgpu_tsg *tsg, u32 timeslice);
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int vgpu_set_sm_exception_type_mask(struct nvgpu_channel *ch,
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u32 exception_mask);
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int vgpu_tsg_set_interleave(struct nvgpu_tsg *tsg, u32 new_level);
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int vgpu_tsg_force_reset_ch(struct nvgpu_channel *ch,
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u32 err_code, bool verbose);
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u32 vgpu_tsg_default_timeslice_us(struct gk20a *g);
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void vgpu_tsg_set_ctx_mmu_error(struct gk20a *g, u32 chid);
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void vgpu_tsg_handle_event(struct gk20a *g,
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struct tegra_vgpu_channel_event_info *info);
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#endif
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