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b80b2bdab8
a. LAUNCH_ERR
- Userspace error.
- Triggered due to faulty launch.
- Handle using recovery to reset CE engine and teardown the
faulty channel.
b. An INVALID_CONFIG -
- Triggered when LCE is mapped to floorswept PCE.
- On iGPU, we use the default PCE 2 LCE HW mapping.
The default mapping can be read from NV_CE_PCE2LCE_CONFIG
INIT value in CE refmanual.
- NvGPU driver configures the mapping on dGPUs (currently only on
Turing).
- So, this interrupt can only be triggered if there is
kernel or HW error
- Recovery ( which is killing the context + engine reset) will
not help resolve this error.
- Trigger Quiesce as part of handling.
c. A MTHD_BUFFER_FAULT -
- NvGPU driver allocates fault buffers for all TSGs or contexts,
maps them in BAR2 VA space and writes the VA into channel
instance block.
- Can be triggered only due to kernel bug
- Recovery will not help, need quiesce
d. FBUF_CRC_FAIL
- Triggered when the CRC entry read from the method fault buffer
does not match the computed CRC from the methods contained in
the buffer.
- This indicates memory corruption and is a fatal interrupt which
at least requires the LCE to be reset before operations can
start again, if not the entire GPU.
- Better to quiesce on memory corruption
CE Engine reset (via recovery) will not help.
e. FBUF_MAGIC_CHK_FAIL
- Triggered when the MAGIC_NUM entry read from the method fault
buf does not match NV_CE_MTHD_BUFFER_GLOBAL_HDR_MAGIC_NUM_VAL
- This indicates memory corruption and is a fatal interrupt
- Better to quiesce on memory corruption
f. STALLING_DEBUG
- Only triggered with SW write for debug purposes
- Debug interrupt, currently ignored
Move launch error handling from GP10b to GV11b HAL as -
1. LAUNCHERR_REPORT errcode METHOD_BUFFER_ACCESS_FAULT is not
defined on Pascal
2. We do not support GP10b on dev-main ToT
JIRA NVGPU-8102
Change-Id: Idc84119bc23b5e85f3479fe62cc8720e98b627a5
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2678893
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
86 lines
2.8 KiB
C
86 lines
2.8 KiB
C
/*
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* GK20A Graphics Copy Engine (gr host)
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*
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* Copyright (c) 2011-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/kmem.h>
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#include <nvgpu/dma.h>
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#include <nvgpu/log.h>
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#include <nvgpu/enabled.h>
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#include <nvgpu/io.h>
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#include <nvgpu/utils.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/cic_mon.h>
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#include <nvgpu/mc.h>
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#include <nvgpu/channel.h>
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#include <nvgpu/engines.h>
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#include "ce2_gk20a.h"
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#include <nvgpu/hw/gk20a/hw_ce2_gk20a.h>
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void gk20a_ce2_stall_isr(struct gk20a *g, u32 inst_id, u32 pri_base,
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bool *needs_rc, bool *needs_quiesce)
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{
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u32 ce2_intr = nvgpu_readl(g, ce2_intr_status_r());
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u32 clear_intr = 0U;
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(void)inst_id;
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(void)pri_base;
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nvgpu_log(g, gpu_dbg_intr, "ce2 isr %08x", ce2_intr);
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/* clear blocking interrupts: they exibit broken behavior */
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if ((ce2_intr & ce2_intr_status_blockpipe_pending_f()) != 0U) {
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nvgpu_log(g, gpu_dbg_intr, "ce2 blocking pipe interrupt");
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clear_intr |= ce2_intr_status_blockpipe_pending_f();
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}
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if ((ce2_intr & ce2_intr_status_launcherr_pending_f()) != 0U) {
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nvgpu_log(g, gpu_dbg_intr, "ce2 launch error interrupt");
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*needs_rc |= true;
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clear_intr |= ce2_intr_status_launcherr_pending_f();
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}
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*needs_quiesce |= false;
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nvgpu_writel(g, ce2_intr_status_r(), clear_intr);
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}
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u32 gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
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{
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u32 ops = 0U;
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u32 ce2_intr = nvgpu_readl(g, ce2_intr_status_r());
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(void)inst_id;
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(void)pri_base;
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nvgpu_log(g, gpu_dbg_intr, "ce2 nonstall isr %08x", ce2_intr);
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if ((ce2_intr & ce2_intr_status_nonblockpipe_pending_f()) != 0U) {
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nvgpu_log(g, gpu_dbg_intr, "ce2 non-blocking pipe interrupt");
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nvgpu_writel(g, ce2_intr_status_r(),
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ce2_intr_status_nonblockpipe_pending_f());
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ops |= (NVGPU_CIC_NONSTALL_OPS_WAKEUP_SEMAPHORE |
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NVGPU_CIC_NONSTALL_OPS_POST_EVENTS);
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}
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return ops;
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}
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