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e81a36e56a
It's preparing to add bellow CFLAGS:
-Werror -Wall -Wextra \
-Wmissing-braces -Wpointer-arith -Wundef \
-Wconversion -Wsign-conversion \
-Wformat-security \
-Wmissing-declarations -Wredundant-decls -Wimplicit-fallthrough
Jira GVSCI-11640
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: Ia16ef186da1e97badff9dd0bf8cbd6700dd77b15
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2555057
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-by: Aparna Das <aparnad@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
70 lines
2.2 KiB
C
70 lines
2.2 KiB
C
/*
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* GK20A Graphics FIFO (gr host)
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*
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* Copyright (c) 2011-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/log.h>
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#include <nvgpu/soc.h>
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#include <nvgpu/io.h>
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#include <nvgpu/fifo.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/power_features/cg.h>
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#include "hal/fifo/fifo_gk20a.h"
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#include <nvgpu/hw/gk20a/hw_fifo_gk20a.h>
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bool gk20a_fifo_find_pbdma_for_runlist(struct gk20a *g,
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u32 runlist_id, u32 *pbdma_mask)
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{
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u32 runlist_bit = BIT32(runlist_id);
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u32 num_pbdmas = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA);
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u32 id;
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*pbdma_mask = 0U;
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for (id = 0U; id < num_pbdmas; id++) {
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u32 pbdma_map = nvgpu_readl(g, fifo_pbdma_map_r(id));
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if ((pbdma_map & runlist_bit) != 0U) {
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*pbdma_mask |= BIT32(id);
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}
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}
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return *pbdma_mask != 0U;
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}
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u32 gk20a_fifo_get_runlist_timeslice(struct gk20a *g)
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{
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(void)g;
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return fifo_runlist_timeslice_timeout_128_f() |
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fifo_runlist_timeslice_timescale_3_f() |
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fifo_runlist_timeslice_enable_true_f();
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}
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u32 gk20a_fifo_get_pb_timeslice(struct gk20a *g)
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{
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(void)g;
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return fifo_pb_timeslice_timeout_16_f() |
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fifo_pb_timeslice_timescale_0_f() |
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fifo_pb_timeslice_enable_true_f();
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}
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