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c8d6a91de6
Moving to use IDs rather than struct makes it reusable on server side. Jira GVSCI-15770 Change-Id: Ibd94ab8c9f0492bd6d20243525905d637eb8de66 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863438 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
81 lines
2.5 KiB
C
81 lines
2.5 KiB
C
/*
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* Copyright (c) 2011-2023, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/log.h>
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#include <nvgpu/channel.h>
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#include <nvgpu/tsg.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/runlist.h>
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#include "hal/fifo/tsg_gk20a.h"
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void gk20a_tsg_enable(struct nvgpu_tsg *tsg)
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{
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struct gk20a *g = tsg->g;
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struct nvgpu_channel *ch;
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if (tsg->runlist == NULL) {
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/*
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* Enabling a TSG that has no runlist (implies no channels)
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* is just a noop.
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*/
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return;
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}
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nvgpu_runlist_set_state(g, BIT32(tsg->runlist->id),
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RUNLIST_DISABLED);
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/*
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* Due to h/w bug that exists in Maxwell and Pascal,
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* we first need to enable all channels with NEXT and CTX_RELOAD set,
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* and then rest of the channels should be enabled
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*/
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nvgpu_rwsem_down_read(&tsg->ch_list_lock);
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nvgpu_list_for_each_entry(ch, &tsg->ch_list, nvgpu_channel, ch_entry) {
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struct nvgpu_channel_hw_state hw_state;
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g->ops.channel.read_state(g, ch->runlist->id, ch->chid,
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&hw_state);
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if (hw_state.next || hw_state.ctx_reload) {
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nvgpu_channel_enable(ch);
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}
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}
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nvgpu_list_for_each_entry(ch, &tsg->ch_list, nvgpu_channel, ch_entry) {
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struct nvgpu_channel_hw_state hw_state;
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g->ops.channel.read_state(g, ch->runlist->id, ch->chid,
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&hw_state);
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if (hw_state.next || hw_state.ctx_reload) {
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continue;
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}
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nvgpu_channel_enable(ch);
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}
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nvgpu_rwsem_up_read(&tsg->ch_list_lock);
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nvgpu_runlist_set_state(g, BIT32(tsg->runlist->id),
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RUNLIST_ENABLED);
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}
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