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ad320f60b9
Implement a hw semaphore which is used to track the gpfifo submission. This is implementation used when the userd.gp_get() is not defined and also the feature flag NVGPU_SUPPORT_SEMA_BASED_GPFIFO_GET is set. At the end of each job submitted, submit a semaphore to write the gpfifo get pointer at hw semaphore addr. At next job submission processing we will read the gpfifo.get from the designated hw semaphore location. JIRA NVGPU-9588 Change-Id: Ic88ace1a3f60e3f38f159e1861464ebcaea04469 Signed-off-by: Ramalingam C <ramalingamc@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2898143 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Sagar Kamble <skamble@nvidia.com> Reviewed-by: Martin Radev <mradev@nvidia.com> Reviewed-by: Ankur Kishore <ankkishore@nvidia.com> Tested-by: Martin Radev <mradev@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
78 lines
2.5 KiB
C
78 lines
2.5 KiB
C
/*
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* GV11B USERD
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*
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* Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/io.h>
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#include <nvgpu/nvgpu_mem.h>
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#include <nvgpu/channel.h>
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#include <nvgpu/hw/gv11b/hw_ram_gv11b.h>
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#include <nvgpu/channel_sync_semaphore.h>
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#include "userd_gv11b.h"
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u32 gv11b_userd_gp_get(struct gk20a *g, struct nvgpu_channel *ch)
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{
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struct nvgpu_mem *mem = ch->userd_mem;
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u32 offset = ch->userd_offset / U32(sizeof(u32));
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u32 ret;
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/*
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* NVGPU_SUPPORT_SEMA_BASED_GPFIFO_GET is enabled when userd get
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* is not getting updated by gpu anymore.
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*/
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if (nvgpu_is_enabled(g, (u32)NVGPU_SUPPORT_SEMA_BASED_GPFIFO_GET)) {
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nvgpu_channel_update_gpfifo_get(ch);
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ret = ch->gpfifo.get;
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} else {
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ret = nvgpu_mem_rd32(g, mem, offset + ram_userd_gp_get_w());
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}
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return ret;
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}
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u64 gv11b_userd_pb_get(struct gk20a *g, struct nvgpu_channel *ch)
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{
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struct nvgpu_mem *mem = ch->userd_mem;
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u32 offset = ch->userd_offset / U32(sizeof(u32));
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u32 lo, hi;
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lo = nvgpu_mem_rd32(g, mem, offset + ram_userd_get_w());
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hi = nvgpu_mem_rd32(g, mem, offset + ram_userd_get_hi_w());
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return ((u64)hi << 32) | lo;
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}
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void gv11b_userd_gp_put(struct gk20a *g, struct nvgpu_channel *ch)
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{
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struct nvgpu_mem *mem = ch->userd_mem;
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u32 offset = ch->userd_offset / U32(sizeof(u32));
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nvgpu_mem_wr32(g, mem, offset + ram_userd_gp_put_w(), ch->gpfifo.put);
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/* Commit everything to GPU. */
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nvgpu_mb();
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g->ops.usermode.ring_doorbell(ch);
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}
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