mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-23 18:16:01 +03:00
9512b9f1de
Remove NVGPU_GPU_IOCTL_ALLOC_AS_FLAGS_USERSPACE_MANAGED and NVGPU_AS_ALLOC_USERSPACE_MANAGED flags which are used for supporting userspace managed address-space. This functionality is not implemented fully in kernel neither going to be implemented in near future. Jira NVGPU-9832 Bug 4034184 Change-Id: I3787d92c44682b02d440e52c7a0c8c0553742dcc Signed-off-by: Shashank Singh <shashsingh@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2882168 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
105 lines
2.9 KiB
C
105 lines
2.9 KiB
C
/*
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* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/bitops.h>
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#include <nvgpu/mm.h>
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#include <nvgpu/vm.h>
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#include "mm_gp10b.h"
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int gp10b_mm_init_bar2_vm(struct gk20a *g)
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{
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int err;
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struct mm_gk20a *mm = &g->mm;
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struct nvgpu_mem *inst_block = &mm->bar2.inst_block;
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u32 big_page_size = g->ops.mm.gmmu.get_default_big_page_size();
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/* BAR2 aperture size is 32MB for chips prior to Ampere */
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if (g->ops.mm.bar2_vm_size != NULL) {
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mm->bar2.aperture_size = g->ops.mm.bar2_vm_size(g);
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} else {
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mm->bar2.aperture_size = U32(32) << 20U;
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}
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nvgpu_log_info(g, "bar2 vm size = 0x%x", mm->bar2.aperture_size);
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mm->bar2.vm = nvgpu_vm_init(g, big_page_size, SZ_4K,
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0ULL, nvgpu_safe_sub_u64(mm->bar2.aperture_size, SZ_4K), 0ULL,
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false, false, "bar2");
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if (mm->bar2.vm == NULL) {
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return -ENOMEM;
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}
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/* allocate instance mem for bar2 */
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err = nvgpu_alloc_inst_block(g, inst_block);
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if (err != 0) {
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goto clean_up_va;
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}
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err = g->ops.mm.init_inst_block_core(inst_block, mm->bar2.vm, big_page_size);
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if (err != 0) {
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nvgpu_free_inst_block(g, inst_block);
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goto clean_up_va;
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}
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return 0;
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clean_up_va:
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nvgpu_vm_put(mm->bar2.vm);
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return err;
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}
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void gp10b_mm_remove_bar2_vm(struct gk20a *g)
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{
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struct mm_gk20a *mm = &g->mm;
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nvgpu_free_inst_block(g, &mm->bar2.inst_block);
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nvgpu_vm_put(mm->bar2.vm);
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}
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void gp10b_mm_get_default_va_sizes(u64 *aperture_size,
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u64 *user_size, u64 *kernel_size)
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{
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/*
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* The maximum GPU VA range supported.
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* Max VA Bits = 49, refer dev_mmu.ref.
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*/
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if (aperture_size != NULL) {
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*aperture_size = BIT64(49);
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}
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/*
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* The default userspace-visible GPU VA size.
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*/
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if (user_size != NULL) {
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*user_size = BIT64(37);
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}
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/*
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* The default kernel-reserved GPU VA size.
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*/
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if (kernel_size != NULL) {
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*kernel_size = BIT64(32);
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}
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}
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