mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-22 17:36:20 +03:00
132 lines
4.6 KiB
C
132 lines
4.6 KiB
C
/*
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* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/nvgpu_init.h>
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#include <nvgpu/nvgpu_err.h>
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#include <nvgpu/nvgpu_err_info.h>
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#include <nvgpu/cic.h>
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#include "cic_priv.h"
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void nvgpu_report_mmu_err(struct gk20a *g, u32 hw_unit, u32 err_id,
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struct mmu_fault_info *fault_info, u32 status, u32 sub_err_type)
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{
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int err = 0;
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struct nvgpu_err_desc *err_desc = NULL;
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struct nvgpu_err_msg err_pkt;
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if (g->ops.cic.report_err == NULL) {
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cic_dbg(g, "CIC does not support reporting error "
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"to safety services");
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return;
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}
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if (hw_unit != NVGPU_ERR_MODULE_HUBMMU) {
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nvgpu_err(g, "invalid hw module (%u)", hw_unit);
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err = -EINVAL;
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goto handle_report_failure;
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}
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err = nvgpu_cic_get_err_desc(g, hw_unit, err_id, &err_desc);
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if (err != 0) {
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nvgpu_err(g, "Failed to get err_desc for "
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"err_id (%u) for hw module (%u)",
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err_id, hw_unit);
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goto handle_report_failure;
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}
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nvgpu_init_mmu_err_msg(&err_pkt);
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err_pkt.hw_unit_id = hw_unit;
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err_pkt.err_id = err_desc->error_id;
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err_pkt.is_critical = err_desc->is_critical;
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err_pkt.err_info.mmu_info.header.sub_err_type = sub_err_type;
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err_pkt.err_info.mmu_info.status = status;
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/* Copy contents of mmu_fault_info */
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if (fault_info != NULL) {
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err_pkt.err_info.mmu_info.info.inst_ptr = fault_info->inst_ptr;
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err_pkt.err_info.mmu_info.info.inst_aperture
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= fault_info->inst_aperture;
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err_pkt.err_info.mmu_info.info.fault_addr
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= fault_info->fault_addr;
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err_pkt.err_info.mmu_info.info.fault_addr_aperture
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= fault_info->fault_addr_aperture;
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err_pkt.err_info.mmu_info.info.timestamp_lo
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= fault_info->timestamp_lo;
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err_pkt.err_info.mmu_info.info.timestamp_hi
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= fault_info->timestamp_hi;
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err_pkt.err_info.mmu_info.info.mmu_engine_id
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= fault_info->mmu_engine_id;
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err_pkt.err_info.mmu_info.info.gpc_id = fault_info->gpc_id;
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err_pkt.err_info.mmu_info.info.client_type
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= fault_info->client_type;
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err_pkt.err_info.mmu_info.info.client_id
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= fault_info->client_id;
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err_pkt.err_info.mmu_info.info.fault_type
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= fault_info->fault_type;
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err_pkt.err_info.mmu_info.info.access_type
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= fault_info->access_type;
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err_pkt.err_info.mmu_info.info.protected_mode
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= fault_info->protected_mode;
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err_pkt.err_info.mmu_info.info.replayable_fault
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= fault_info->replayable_fault;
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err_pkt.err_info.mmu_info.info.replay_fault_en
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= fault_info->replay_fault_en;
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err_pkt.err_info.mmu_info.info.valid = fault_info->valid;
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err_pkt.err_info.mmu_info.info.faulted_pbdma =
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fault_info->faulted_pbdma;
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err_pkt.err_info.mmu_info.info.faulted_engine =
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fault_info->faulted_engine;
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err_pkt.err_info.mmu_info.info.faulted_subid =
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fault_info->faulted_subid;
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err_pkt.err_info.mmu_info.info.chid = fault_info->chid;
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}
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err_pkt.err_desc = err_desc;
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err_pkt.err_size = nvgpu_safe_cast_u64_to_u8(
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sizeof(err_pkt.err_info.mmu_info));
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if (g->ops.cic.report_err != NULL) {
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err = g->ops.cic.report_err(g, (void *)&err_pkt,
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sizeof(err_pkt), err_desc->is_critical);
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if (err != 0) {
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nvgpu_err(g, "Failed to report MMU fault: hw_unit=%u, "
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"err_id=%u, sub_err_type=%u, status=%u",
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hw_unit, err_id, sub_err_type, status);
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}
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}
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handle_report_failure:
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if (err != 0) {
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nvgpu_sw_quiesce(g);
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}
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}
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void nvgpu_inject_mmu_swerror(struct gk20a *g, u32 hw_unit, u32 err_index,
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u32 sub_err_type)
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{
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u32 status = 0U;
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struct mmu_fault_info fault_info;
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(void) memset(&fault_info, ERR_INJECT_TEST_PATTERN, sizeof(fault_info));
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nvgpu_report_mmu_err(g, hw_unit, err_index,
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&fault_info, status, sub_err_type);
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}
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