mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-22 17:36:20 +03:00
145 lines
3.9 KiB
C
145 lines
3.9 KiB
C
/*
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* Copyright (c) 2018-2020, NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/debugfs.h>
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#include <linux/seq_file.h>
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#include "os_linux.h"
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#include <nvgpu/boardobjgrp_e32.h>
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#include <nvgpu/boardobjgrp_e255.h>
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#include <nvgpu/pmu/clk/clk.h>
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#include <nvgpu/pmu/volt.h>
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/* Dependency of this include will be removed in further CL */
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#include "../../common/pmu/boardobj/boardobj.h"
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#include "hal/clk/clk_tu104.h"
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void nvgpu_clk_arb_pstate_change_lock(struct gk20a *g, bool lock);
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static int tu104_get_rate_show(void *data , u64 *val)
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{
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struct namemap_cfg *c = (struct namemap_cfg *)data;
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struct gk20a *g = c->g;
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if (!g->ops.clk.get_rate_cntr)
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return -EINVAL;
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*val = c->is_counter ? (u64)c->scale * g->ops.clk.get_rate_cntr(g, c) :
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0 /* TODO PLL read */;
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return 0;
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}
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DEFINE_SIMPLE_ATTRIBUTE(get_rate_fops, tu104_get_rate_show, NULL, "%llu\n");
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static int vftable_show(struct seq_file *s, void *unused)
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{
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struct gk20a *g = s->private;
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int status;
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u8 index;
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u32 voltage_min_uv, voltage_step_size_uv;
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u32 gpcclk_clkmhz = 0, gpcclk_voltuv = 0;
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voltage_min_uv = nvgpu_pmu_clk_fll_get_lut_step_size(g->pmu->clk_pmu);
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voltage_step_size_uv = nvgpu_pmu_clk_fll_get_lut_step_size(g->pmu->clk_pmu);
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for (index = 0; index < CTRL_CLK_LUT_NUM_ENTRIES_GV10x; index++) {
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gpcclk_voltuv = voltage_min_uv + index * voltage_step_size_uv;
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status = nvgpu_clk_domain_volt_to_freq(g, 0, &gpcclk_clkmhz,
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&gpcclk_voltuv, CTRL_VOLT_DOMAIN_LOGIC);
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if (status != 0) {
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nvgpu_err(g, "Failed to get freq for requested volt");
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return status;
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}
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seq_printf(s, "Voltage: %duV Frequency: %dMHz\n",
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gpcclk_voltuv, gpcclk_clkmhz);
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}
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return 0;
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}
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static int vftable_open(struct inode *inode, struct file *file)
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{
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return single_open(file, vftable_show, inode->i_private);
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}
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static const struct file_operations vftable_fops = {
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.open = vftable_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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};
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static int tu104_change_seq_time(void *data , u64 *val)
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{
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struct gk20a *g = (struct gk20a *)data;
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s64 readval;
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if (!g->ops.clk.get_change_seq_time)
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return -EINVAL;
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g->ops.clk.get_change_seq_time(g, &readval);
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*val = (u64)readval;
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return 0;
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}
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DEFINE_SIMPLE_ATTRIBUTE(change_seq_fops, tu104_change_seq_time, NULL, "%llu\n");
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int tu104_clk_init_debugfs(struct gk20a *g)
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{
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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struct dentry *gpu_root = l->debugfs;
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struct dentry *clocks_root, *clk_freq_ctlr_root;
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struct dentry *d;
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unsigned int i;
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if (NULL == (clocks_root = debugfs_create_dir("clocks", gpu_root)))
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return -ENOMEM;
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clk_freq_ctlr_root = debugfs_create_dir("clk_freq_ctlr", gpu_root);
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if (clk_freq_ctlr_root == NULL)
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return -ENOMEM;
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d = debugfs_create_file("change_seq_time_us", S_IRUGO, clocks_root,
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g, &change_seq_fops);
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nvgpu_log(g, gpu_dbg_info, "g=%p", g);
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for (i = 0; i < g->clk.namemap_num; i++) {
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if (g->clk.clk_namemap[i].is_enable) {
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d = debugfs_create_file(
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g->clk.clk_namemap[i].name,
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S_IRUGO,
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clocks_root,
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&g->clk.clk_namemap[i],
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&get_rate_fops);
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if (!d)
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goto err_out;
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}
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}
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d = debugfs_create_file("vftable", S_IRUGO,
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clocks_root, g, &vftable_fops);
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if (!d)
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goto err_out;
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return 0;
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err_out:
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pr_err("%s: Failed to make debugfs node\n", __func__);
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debugfs_remove_recursive(clocks_root);
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return -ENOMEM;
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}
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