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- if L2 flush is done when ELPG_MS feature is engaged then it can cause some of the signals to go non-idle. This can cause idle snap in ELPG_MS. - To avoid the idle snap, add elpg_ms protected call before L2 flush operation Bug 200763448 Change-Id: I651875bc051c3b7d26d2bb0b593083512a5765b2 Signed-off-by: Divya <dsinghatwari@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2599459 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
246 lines
6.4 KiB
C
246 lines
6.4 KiB
C
/*
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* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <linux/dma-buf.h>
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#include <uapi/linux/nvgpu.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/vm.h>
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#include <nvgpu/vm_remap.h>
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#include <nvgpu/nvgpu_sgt.h>
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#include <nvgpu/power_features/pg.h>
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#include "os_linux.h"
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#include "dmabuf_priv.h"
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#define dev_from_vm(vm) dev_from_gk20a(vm->mm->g)
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u64 nvgpu_vm_remap_get_handle(struct nvgpu_vm_remap_os_buffer *remap_os_buf)
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{
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return (u64)(uintptr_t)remap_os_buf->os_priv.dmabuf;
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}
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int nvgpu_vm_remap_os_buf_get(struct vm_gk20a *vm,
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struct nvgpu_vm_remap_op *op,
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struct nvgpu_vm_remap_os_buffer *remap_os_buf)
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{
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struct gk20a *g = gk20a_from_vm(vm);
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struct device *dev = dev_from_gk20a(g);
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struct dma_buf *dmabuf;
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struct sg_table *sgt = NULL;
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struct nvgpu_sgt *nv_sgt = NULL;
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struct dma_buf_attachment *attachment;
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enum nvgpu_aperture aperture;
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enum dma_data_direction dmabuf_direction;
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int err = 0;
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/* get ref to the dmabuf fd */
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dmabuf = dma_buf_get(op->mem_handle);
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if (IS_ERR(dmabuf)) {
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nvgpu_warn(g, "mem_handle 0x%x is not a dmabuf",
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op->mem_handle);
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return -EINVAL;
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}
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if (!(dmabuf->file->f_mode & (FMODE_WRITE | FMODE_PWRITE)) &&
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!(op->flags & NVGPU_VM_REMAP_OP_FLAGS_ACCESS_NO_WRITE)) {
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nvgpu_err(g, "RW access requested for RO mapped buffer");
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err = -EINVAL;
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goto clean_up;
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}
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if ((op->flags & NVGPU_VM_REMAP_OP_FLAGS_ACCESS_NO_WRITE) != 0) {
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dmabuf_direction = DMA_TO_DEVICE;
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} else {
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dmabuf_direction = DMA_BIDIRECTIONAL;
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}
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sgt = nvgpu_mm_pin(dev, dmabuf, &attachment, dmabuf_direction);
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if (IS_ERR(sgt)) {
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nvgpu_warn(g, "failed to pin dma_buf");
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err = -ENOMEM;
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goto clean_up;
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}
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aperture = gk20a_dmabuf_aperture(g, dmabuf);
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if (aperture == APERTURE_INVALID) {
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err = -EINVAL;
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goto clean_up;
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}
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nv_sgt = nvgpu_linux_sgt_create(g, sgt);
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if (nv_sgt == NULL) {
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nvgpu_warn(g, "failed to create nv_sgt");
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err = -ENOMEM;
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goto clean_up;
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}
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memset(remap_os_buf, 0, sizeof(*remap_os_buf));
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remap_os_buf->os_priv.dmabuf = dmabuf;
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remap_os_buf->os_priv.attachment = attachment;
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remap_os_buf->os_priv.sgt = sgt;
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remap_os_buf->os_buf.dmabuf = dmabuf;
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remap_os_buf->os_buf.attachment = attachment;
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remap_os_buf->os_buf.dev = dev;
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remap_os_buf->nv_sgt = nv_sgt;
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remap_os_buf->aperture = aperture;
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return 0;
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clean_up:
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if (nv_sgt != NULL) {
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nvgpu_sgt_free(g, nv_sgt);
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}
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if (IS_ERR(sgt)) {
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nvgpu_mm_unpin(dev, dmabuf, attachment, sgt);
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}
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dma_buf_put(dmabuf);
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return err;
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}
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void nvgpu_vm_remap_os_buf_put(struct vm_gk20a *vm,
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struct nvgpu_vm_remap_os_buffer *remap_os_buf)
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{
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struct gk20a *g = gk20a_from_vm(vm);
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struct device *dev = dev_from_gk20a(g);
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struct gk20a_comptags comptags;
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int err = 0;
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nvgpu_mm_unpin(dev, remap_os_buf->os_priv.dmabuf,
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remap_os_buf->os_priv.attachment, remap_os_buf->os_priv.sgt);
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gk20a_get_comptags(&remap_os_buf->os_buf, &comptags);
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/*
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* Flush compression bit cache before releasing the physical
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* memory buffer reference.
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*/
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if (comptags.offset != 0) {
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g->ops.cbc.ctrl(g, nvgpu_cbc_op_clean, 0, 0);
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err = nvgpu_pg_elpg_ms_protected_call(g,
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g->ops.mm.cache.l2_flush(g, true));
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if (err != 0) {
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nvgpu_err(g, "l2 flush failed");
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return;
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}
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}
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nvgpu_sgt_free(g, remap_os_buf->nv_sgt);
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dma_buf_put(remap_os_buf->os_priv.dmabuf);
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}
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static int nvgpu_vm_remap_validate_map_op(struct nvgpu_as_remap_op *op)
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{
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int err = 0;
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u32 valid_flags = (NVGPU_AS_REMAP_OP_FLAGS_CACHEABLE |
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NVGPU_AS_REMAP_OP_FLAGS_ACCESS_NO_WRITE);
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if ((op->flags & ~valid_flags) != 0) {
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err = -EINVAL;
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}
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return err;
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}
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static int nvgpu_vm_remap_validate_unmap_op(struct nvgpu_as_remap_op *op)
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{
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int err = 0;
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if ((op->compr_kind != NVGPU_KIND_INVALID) ||
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(op->incompr_kind != NVGPU_KIND_INVALID) ||
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(op->flags != 0) ||
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(op->mem_offset_in_pages != 0)) {
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err = -EINVAL;
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}
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return err;
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}
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static u32 nvgpu_vm_remap_translate_as_flags(u32 flags)
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{
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u32 core_flags = 0;
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if ((flags & NVGPU_AS_REMAP_OP_FLAGS_CACHEABLE) != 0) {
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core_flags |= NVGPU_VM_REMAP_OP_FLAGS_CACHEABLE;
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}
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if ((flags & NVGPU_AS_REMAP_OP_FLAGS_ACCESS_NO_WRITE) != 0) {
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core_flags |= NVGPU_VM_REMAP_OP_FLAGS_ACCESS_NO_WRITE;
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}
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return core_flags;
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}
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int nvgpu_vm_remap_translate_as_op(struct vm_gk20a *vm,
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struct nvgpu_vm_remap_op *vm_op,
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struct nvgpu_as_remap_op *as_op)
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{
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int err = 0;
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u64 page_size;
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u64 max_num_pages;
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if (as_op->mem_handle == 0) {
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err = nvgpu_vm_remap_validate_unmap_op(as_op);
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} else {
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err = nvgpu_vm_remap_validate_map_op(as_op);
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}
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if (err != 0)
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goto clean_up;
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page_size = vm->gmmu_page_sizes[GMMU_PAGE_SIZE_BIG];
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max_num_pages = (ULONG_MAX / page_size);
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if ((as_op->num_pages == 0) ||
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(as_op->num_pages > max_num_pages) ||
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(as_op->mem_offset_in_pages > max_num_pages) ||
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(as_op->virt_offset_in_pages > max_num_pages)) {
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err = -EINVAL;
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goto clean_up;
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}
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vm_op->flags = nvgpu_vm_remap_translate_as_flags(as_op->flags);
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vm_op->compr_kind = as_op->compr_kind;
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vm_op->incompr_kind = as_op->incompr_kind;
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vm_op->mem_handle = as_op->mem_handle;
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vm_op->mem_offset_in_pages = as_op->mem_offset_in_pages;
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vm_op->virt_offset_in_pages = as_op->virt_offset_in_pages;
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vm_op->num_pages = as_op->num_pages;
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return 0;
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clean_up:
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return err;
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}
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void nvgpu_vm_remap_translate_vm_op(struct nvgpu_as_remap_op *as_op,
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struct nvgpu_vm_remap_op *vm_op)
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{
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as_op->compr_kind = vm_op->compr_kind;
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as_op->incompr_kind = vm_op->incompr_kind;
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}
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