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RSTG_ECC errors are not expected to occur in gv11b since it does not contains R-stage memory. Hence, the reporting of this error has been replaced with BUG(). CE_NONBLOCK_PIPE interrupt is used for notification of completion of copy operation and it is not an error interrupt. Further, this notification has not been used by CUDA. So, the reporting of CE NONBLOCK_PIPE has been removed. JIRA NVGPU-6124 Bug 200616002 Change-Id: Idf027cc27cf854188503d4d4f07d0f54af1da164 Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2427125 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Shashank Singh <shashsingh@nvidia.com> Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
77 lines
2.6 KiB
C
77 lines
2.6 KiB
C
/*
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* Pascal GPU series Copy Engine.
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*
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* Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/mc.h>
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#include <nvgpu/nvgpu_err.h>
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#include "ce_gp10b.h"
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#include <nvgpu/hw/gp10b/hw_ce_gp10b.h>
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void gp10b_ce_stall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
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{
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u32 ce_intr = nvgpu_readl(g, ce_intr_status_r(inst_id));
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u32 clear_intr = 0U;
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nvgpu_log(g, gpu_dbg_intr, "ce isr %08x %08x", ce_intr, inst_id);
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/* clear blocking interrupts: they exibit broken behavior */
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if ((ce_intr & ce_intr_status_blockpipe_pending_f()) != 0U) {
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nvgpu_report_ce_err(g, NVGPU_ERR_MODULE_CE, inst_id,
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GPU_CE_BLOCK_PIPE, ce_intr);
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nvgpu_err(g, "ce blocking pipe interrupt");
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clear_intr |= ce_intr_status_blockpipe_pending_f();
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}
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if ((ce_intr & ce_intr_status_launcherr_pending_f()) != 0U) {
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nvgpu_report_ce_err(g, NVGPU_ERR_MODULE_CE, inst_id,
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GPU_CE_LAUNCH_ERROR, ce_intr);
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nvgpu_err(g, "ce launch error interrupt");
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clear_intr |= ce_intr_status_launcherr_pending_f();
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}
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nvgpu_writel(g, ce_intr_status_r(inst_id), clear_intr);
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return;
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}
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u32 gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
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{
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u32 ops = 0U;
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u32 ce_intr = nvgpu_readl(g, ce_intr_status_r(inst_id));
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nvgpu_log(g, gpu_dbg_intr, "ce nonstall isr %08x %08x",
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ce_intr, inst_id);
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if ((ce_intr & ce_intr_status_nonblockpipe_pending_f()) != 0U) {
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nvgpu_writel(g, ce_intr_status_r(inst_id),
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ce_intr_status_nonblockpipe_pending_f());
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ops |= (NVGPU_NONSTALL_OPS_WAKEUP_SEMAPHORE |
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NVGPU_NONSTALL_OPS_POST_EVENTS);
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}
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return ops;
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}
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