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d5d31e5b17
Fix rule 8.6 misra violation in ltc code by enclosing following functions defs under CONFIG_NVGPU_FALCON_NON_FUSA switch. gp10b_ltc_intr_configure gp10b_ltc_intr_isr gm20b_determine_L2_size_bytes gm20b_ltc_set_enabled gm20b_ltc_init_fs_state Added following functions defs under CONFIG_NVGPU_INJECT_HWERR switch. gv11b_ltc_get_err_desc gv11b_ltc_inject_ecc_error Also added hal initializations under relevant switch. JIRA NVGPU-3872 Change-Id: I6800ae4a8fcd91e534df97e8db7770f0e4e9112a Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2174827 GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>