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cc9f3d80e3
linux driver runs in user's process but qnx driver has dedicate driver process, so they have different way to get user pid. nvgpu common code expect calls from os specific code pass pid/tid. ce/cde open channel for internal use, we use driver pid. Jira VQRM-3534 Change-Id: I892372ac5f1dc4d25f9928d16992bcc659d12a56 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1694145 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
111 lines
3.2 KiB
C
111 lines
3.2 KiB
C
/*
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* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __TSG_GK20A_H_
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#define __TSG_GK20A_H_
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#include <nvgpu/lock.h>
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#include <nvgpu/kref.h>
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#include <nvgpu/rwsem.h>
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#include "gr_gk20a.h"
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#define NVGPU_INVALID_TSG_ID (-1)
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struct channel_gk20a;
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bool gk20a_is_channel_marked_as_tsg(struct channel_gk20a *ch);
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struct tsg_gk20a *gk20a_tsg_open(struct gk20a *g, pid_t pid);
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void gk20a_tsg_release(struct nvgpu_ref *ref);
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int gk20a_init_tsg_support(struct gk20a *g, u32 tsgid);
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struct tsg_gk20a *tsg_gk20a_from_ch(struct channel_gk20a *ch);
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struct tsg_gk20a {
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struct gk20a *g;
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bool in_use;
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int tsgid;
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struct nvgpu_ref refcount;
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struct nvgpu_list_node ch_list;
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int num_active_channels;
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struct nvgpu_rwsem ch_list_lock;
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unsigned int timeslice_us;
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unsigned int timeslice_timeout;
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unsigned int timeslice_scale;
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struct vm_gk20a *vm;
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u32 interleave_level;
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struct nvgpu_list_node event_id_list;
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struct nvgpu_mutex event_id_list_lock;
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u32 runlist_id;
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pid_t tgid;
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struct nvgpu_mem *eng_method_buffers;
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u32 num_active_tpcs;
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u8 tpc_pg_enabled;
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bool tpc_num_initialized;
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struct nvgpu_gr_ctx gr_ctx;
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};
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int gk20a_enable_tsg(struct tsg_gk20a *tsg);
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int gk20a_disable_tsg(struct tsg_gk20a *tsg);
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int gk20a_tsg_bind_channel(struct tsg_gk20a *tsg,
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struct channel_gk20a *ch);
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int gk20a_tsg_unbind_channel(struct channel_gk20a *ch);
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void gk20a_tsg_event_id_post_event(struct tsg_gk20a *tsg,
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int event_id);
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int gk20a_tsg_set_runlist_interleave(struct tsg_gk20a *tsg, u32 level);
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int gk20a_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice);
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u32 gk20a_tsg_get_timeslice(struct tsg_gk20a *tsg);
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int gk20a_tsg_set_priority(struct gk20a *g, struct tsg_gk20a *tsg,
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u32 priority);
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struct gk20a_event_id_data {
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struct gk20a *g;
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int id; /* ch or tsg */
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int pid;
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u32 event_id;
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bool event_posted;
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struct nvgpu_cond event_id_wq;
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struct nvgpu_mutex lock;
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struct nvgpu_list_node event_id_node;
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};
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static inline struct gk20a_event_id_data *
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gk20a_event_id_data_from_event_id_node(struct nvgpu_list_node *node)
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{
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return (struct gk20a_event_id_data *)
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((uintptr_t)node - offsetof(struct gk20a_event_id_data, event_id_node));
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};
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#endif /* __TSG_GK20A_H_ */
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