mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-23 18:16:01 +03:00
8a1d51fe49
- Added support for single rail multi step volt policy & below
are the list of define & struct added/updated to support same.
CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL_MULTI_STEP 0x04,
NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL_MULTI_STEP 0x04,
Updated struct vbios_voltage_policy_table_1x_entry,
struct nv_pmu_volt_volt_policy_sr_multi_step_boardobj_set, this holds
members which help to config single rail multi step like delay
between switch step, ramp up & ramp down step size in uv.
- Added case to support SINGLE_RAIL_MULTI_STEP in
volt_volt_policy_construct() based on boardobj type.
- Added case to support SINGLE_RAIL_MULTI_STEP in
volt_get_volt_policy_table() to read data from VBIOS
table vbios_voltage_policy_table_1x_entry & extract to
voltage_policy_single_rail_multi_step.
- Added methods to forward single rail multi step data to
PMU using below methods by assigning data read from
VBIOS voltage_policy_single_rail_multi_step to
nv_pmu_volt_volt_policy_sr_multi_step_boardobj_set
interface.
volt_construct_volt_policy_single_rail_multi_step()
volt_policy_pmu_data_init_sr_multi_step()
volt_policy_pmu_data_init_single_rail()
construct_volt_policy_single_rail()
Change-Id: I17bc8c320777191611365ee63274c38ffe5ecbf7
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1660687
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
403 lines
11 KiB
C
403 lines
11 KiB
C
/*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _GPMUIFVOLT_H_
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#define _GPMUIFVOLT_H_
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#include "gpmuifboardobj.h"
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#include <nvgpu/flcnif_cmn.h>
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#include "ctrl/ctrlvolt.h"
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#define NV_PMU_VOLT_VALUE_0V_IN_UV (0)
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/* ------------- VOLT_RAIL's GRP_SET defines and structures ------------- */
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#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_RAIL 0x00
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#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_DEVICE 0x01
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#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_POLICY 0x02
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struct nv_pmu_volt_volt_rail_boardobjgrp_set_header {
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struct nv_pmu_boardobjgrp_e32 super;
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};
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struct nv_pmu_volt_volt_rail_boardobj_set {
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struct nv_pmu_boardobj super;
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u8 rel_limit_vfe_equ_idx;
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u8 alt_rel_limit_vfe_equ_idx;
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u8 ov_limit_vfe_equ_idx;
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u8 vmin_limit_vfe_equ_idx;
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u8 volt_margin_limit_vfe_equ_idx;
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u8 pwr_equ_idx;
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u8 volt_dev_idx_default;
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u8 volt_dev_idx_ipc_vmin;
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u8 volt_scale_exp_pwr_equ_idx;
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struct ctrl_boardobjgrp_mask_e32 volt_dev_mask;
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s32 volt_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES];
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};
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union nv_pmu_volt_volt_rail_boardobj_set_union {
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struct nv_pmu_boardobj board_obj;
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struct nv_pmu_volt_volt_rail_boardobj_set super;
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};
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NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_rail);
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/* ------------ VOLT_DEVICE's GRP_SET defines and structures ------------ */
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struct nv_pmu_volt_volt_device_boardobjgrp_set_header {
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struct nv_pmu_boardobjgrp_e32 super;
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};
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struct nv_pmu_volt_volt_device_boardobj_set {
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struct nv_pmu_boardobj super;
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u32 switch_delay_us;
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u32 voltage_min_uv;
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u32 voltage_max_uv;
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u32 volt_step_uv;
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};
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struct nv_pmu_volt_volt_device_vid_boardobj_set {
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struct nv_pmu_volt_volt_device_boardobj_set super;
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s32 voltage_base_uv;
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s32 voltage_offset_scale_uv;
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u8 gpio_pin[CTRL_VOLT_VOLT_DEV_VID_VSEL_MAX_ENTRIES];
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u8 vsel_mask;
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};
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struct nv_pmu_volt_volt_device_pwm_boardobj_set {
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struct nv_pmu_volt_volt_device_boardobj_set super;
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u32 raw_period;
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s32 voltage_base_uv;
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s32 voltage_offset_scale_uv;
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enum nv_pmu_pmgr_pwm_source pwm_source;
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};
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union nv_pmu_volt_volt_device_boardobj_set_union {
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struct nv_pmu_boardobj board_obj;
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struct nv_pmu_volt_volt_device_boardobj_set super;
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struct nv_pmu_volt_volt_device_vid_boardobj_set vid;
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struct nv_pmu_volt_volt_device_pwm_boardobj_set pwm;
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};
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NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_device);
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/* ------------ VOLT_POLICY's GRP_SET defines and structures ------------ */
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struct nv_pmu_volt_volt_policy_boardobjgrp_set_header {
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struct nv_pmu_boardobjgrp_e32 super;
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u8 perf_core_vf_seq_policy_idx;
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};
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struct nv_pmu_volt_volt_policy_boardobj_set {
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struct nv_pmu_boardobj super;
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};
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struct nv_pmu_volt_volt_policy_sr_boardobj_set {
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struct nv_pmu_volt_volt_policy_boardobj_set super;
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u8 rail_idx;
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};
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struct nv_pmu_volt_volt_policy_sr_multi_step_boardobj_set {
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struct nv_pmu_volt_volt_policy_sr_boardobj_set super;
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u16 inter_switch_delay_us;
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u32 ramp_up_step_size_uv;
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u32 ramp_down_step_size_uv;
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};
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struct nv_pmu_volt_volt_policy_splt_r_boardobj_set {
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struct nv_pmu_volt_volt_policy_boardobj_set super;
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u8 rail_idx_master;
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u8 rail_idx_slave;
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u8 delta_min_vfe_equ_idx;
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u8 delta_max_vfe_equ_idx;
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s32 offset_delta_min_uv;
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s32 offset_delta_max_uv;
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};
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struct nv_pmu_volt_volt_policy_srms_boardobj_set {
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struct nv_pmu_volt_volt_policy_splt_r_boardobj_set super;
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u16 inter_switch_delayus;
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};
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/* sr - > single_rail */
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struct nv_pmu_volt_volt_policy_srss_boardobj_set {
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struct nv_pmu_volt_volt_policy_splt_r_boardobj_set super;
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};
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union nv_pmu_volt_volt_policy_boardobj_set_union {
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struct nv_pmu_boardobj board_obj;
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struct nv_pmu_volt_volt_policy_boardobj_set super;
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struct nv_pmu_volt_volt_policy_sr_boardobj_set single_rail;
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struct nv_pmu_volt_volt_policy_sr_multi_step_boardobj_set
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single_rail_ms;
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struct nv_pmu_volt_volt_policy_splt_r_boardobj_set split_rail;
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struct nv_pmu_volt_volt_policy_srms_boardobj_set
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split_rail_m_s;
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struct nv_pmu_volt_volt_policy_srss_boardobj_set
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split_rail_s_s;
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};
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NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_policy);
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/* ----------- VOLT_RAIL's GRP_GET_STATUS defines and structures ----------- */
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struct nv_pmu_volt_volt_rail_boardobjgrp_get_status_header {
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struct nv_pmu_boardobjgrp_e32 super;
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};
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struct nv_pmu_volt_volt_rail_boardobj_get_status {
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struct nv_pmu_boardobj_query super;
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u32 curr_volt_defaultu_v;
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u32 rel_limitu_v;
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u32 alt_rel_limitu_v;
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u32 ov_limitu_v;
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u32 max_limitu_v;
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u32 vmin_limitu_v;
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s32 volt_margin_limitu_v;
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u32 rsvd;
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};
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union nv_pmu_volt_volt_rail_boardobj_get_status_union {
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struct nv_pmu_boardobj_query board_obj;
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struct nv_pmu_volt_volt_rail_boardobj_get_status super;
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};
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NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(volt, volt_rail);
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/* ---------- VOLT_DEVICE's GRP_GET_STATUS defines and structures ---------- */
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struct nv_pmu_volt_volt_device_boardobjgrp_get_status_header {
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struct nv_pmu_boardobjgrp_e32 super;
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};
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struct nv_pmu_volt_volt_device_boardobj_get_status {
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struct nv_pmu_boardobj_query super;
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};
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union nv_pmu_volt_volt_device_boardobj_get_status_union {
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struct nv_pmu_boardobj_query board_obj;
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struct nv_pmu_volt_volt_device_boardobj_get_status super;
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};
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NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(volt, volt_device);
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/* ---------- VOLT_POLICY's GRP_GET_STATUS defines and structures ---------- */
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struct nv_pmu_volt_volt_policy_boardobjgrp_get_status_header {
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struct nv_pmu_boardobjgrp_e32 super;
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};
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struct nv_pmu_volt_volt_policy_boardobj_get_status {
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struct nv_pmu_boardobj_query super;
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u32 offset_volt_requ_v;
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u32 offset_volt_curru_v;
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};
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struct nv_pmu_volt_volt_policy_sr_boardobj_get_status {
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struct nv_pmu_volt_volt_policy_boardobj_get_status super;
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u32 curr_voltu_v;
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};
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struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status {
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struct nv_pmu_volt_volt_policy_boardobj_get_status super;
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s32 delta_minu_v;
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s32 delta_maxu_v;
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s32 orig_delta_minu_v;
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s32 orig_delta_maxu_v;
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u32 curr_volt_masteru_v;
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u32 curr_volt_slaveu_v;
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bool b_violation;
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};
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/* srms -> split_rail_multi_step */
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struct nv_pmu_volt_volt_policy_srms_boardobj_get_status {
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struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status super;
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};
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/* srss -> split_rail_single_step */
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struct nv_pmu_volt_volt_policy_srss_boardobj_get_status {
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struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status super;
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};
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union nv_pmu_volt_volt_policy_boardobj_get_status_union {
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struct nv_pmu_boardobj_query board_obj;
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struct nv_pmu_volt_volt_policy_boardobj_get_status super;
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struct nv_pmu_volt_volt_policy_sr_boardobj_get_status single_rail;
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struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status split_rail;
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struct nv_pmu_volt_volt_policy_srms_boardobj_get_status
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split_rail_m_s;
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struct nv_pmu_volt_volt_policy_srss_boardobj_get_status
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split_rail_s_s;
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};
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NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(volt, volt_policy);
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struct nv_pmu_volt_policy_voltage_data {
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u8 policy_idx;
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struct ctrl_perf_volt_rail_list
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rail_list;
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};
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struct nv_pmu_volt_rail_get_voltage {
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u8 rail_idx;
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u32 voltage_uv;
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};
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struct nv_pmu_volt_volt_rail_set_noise_unaware_vmin {
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u8 num_rails;
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struct ctrl_volt_volt_rail_list
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rail_list;
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};
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#define NV_PMU_VOLT_CMD_ID_BOARDOBJ_GRP_SET (0x00000000)
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#define NV_PMU_VOLT_CMD_ID_RPC (0x00000001)
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#define NV_PMU_VOLT_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002)
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#define NV_PMU_VOLT_RPC_ID_VOLT_RAIL_SET_NOISE_UNAWARE_VMIN (0x00000004)
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/*!
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* PMU VOLT RPC calls.
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*/
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#define NV_PMU_VOLT_RPC_ID_LOAD (0x00000000)
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#define NV_PMU_VOLT_RPC_ID_VOLT_POLICY_SET_VOLTAGE (0x00000002)
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#define NV_PMU_VOLT_RPC_ID_VOLT_RAIL_GET_VOLTAGE (0x00000003)
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struct nv_pmu_volt_cmd_rpc {
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u8 cmd_type;
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u8 pad[3];
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struct nv_pmu_allocation request;
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};
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#define NV_PMU_VOLT_CMD_RPC_ALLOC_OFFSET \
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offsetof(struct nv_pmu_volt_cmd_rpc, request)
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struct nv_pmu_volt_cmd {
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union {
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u8 cmd_type;
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struct nv_pmu_boardobj_cmd_grp grp_set;
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struct nv_pmu_volt_cmd_rpc rpc;
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struct nv_pmu_boardobj_cmd_grp grp_get_status;
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};
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};
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struct nv_pmu_volt_rpc {
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u8 function;
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bool b_supported;
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bool b_success;
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flcn_status flcn_status;
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union {
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struct nv_pmu_volt_policy_voltage_data volt_policy_voltage_data;
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struct nv_pmu_volt_rail_get_voltage volt_rail_get_voltage;
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struct nv_pmu_volt_volt_rail_set_noise_unaware_vmin
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volt_rail_set_noise_unaware_vmin;
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} params;
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};
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/*!
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* VOLT MSG ID definitions
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*/
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#define NV_PMU_VOLT_MSG_ID_BOARDOBJ_GRP_SET (0x00000000)
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#define NV_PMU_VOLT_MSG_ID_RPC (0x00000001)
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#define NV_PMU_VOLT_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002)
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/*!
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* Message carrying the result of the VOLT RPC execution.
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*/
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struct nv_pmu_volt_msg_rpc {
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u8 msg_type;
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u8 rsvd[3];
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struct nv_pmu_allocation response;
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};
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#define NV_PMU_VOLT_MSG_RPC_ALLOC_OFFSET \
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offsetof(struct nv_pmu_volt_msg_rpc, response)
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struct nv_pmu_volt_msg {
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union {
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u8 msg_type;
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struct nv_pmu_boardobj_msg_grp grp_set;
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struct nv_pmu_volt_msg_rpc rpc;
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struct nv_pmu_boardobj_msg_grp grp_get_status;
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};
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};
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#define NV_PMU_VF_INJECT_MAX_VOLT_RAILS (2)
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struct nv_pmu_volt_volt_rail_list {
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u8 num_rails;
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struct ctrl_perf_volt_rail_list_item
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rails[NV_PMU_VF_INJECT_MAX_VOLT_RAILS];
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};
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struct nv_pmu_volt_volt_rail_list_V1 {
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u8 num_rails;
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struct ctrl_volt_volt_rail_list_item_v1
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rails[NV_PMU_VF_INJECT_MAX_VOLT_RAILS];
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};
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/* VOLT RPC */
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#define NV_PMU_RPC_ID_VOLT_BOARD_OBJ_GRP_CMD 0x00
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#define NV_PMU_RPC_ID_VOLT_VOLT_SET_VOLTAGE 0x01
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#define NV_PMU_RPC_ID_VOLT_LOAD 0x02
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#define NV_PMU_RPC_ID_VOLT_VOLT_RAIL_GET_VOLTAGE 0x03
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#define NV_PMU_RPC_ID_VOLT_VOLT_POLICY_SANITY_CHECK 0x04
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#define NV_PMU_RPC_ID_VOLT_TEST_EXECUTE 0x05
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#define NV_PMU_RPC_ID_VOLT__COUNT 0x06
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/*
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* Defines the structure that holds data
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* used to execute LOAD RPC.
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*/
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struct nv_pmu_rpc_struct_volt_load {
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/*[IN/OUT] Must be first field in RPC structure */
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struct nv_pmu_rpc_header hdr;
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u32 scratch[1];
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};
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/*
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* Defines the structure that holds data
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* used to execute VOLT_SET_VOLTAGE RPC.
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*/
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struct nv_pmu_rpc_struct_volt_volt_set_voltage {
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/*[IN/OUT] Must be first field in RPC structure */
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struct nv_pmu_rpc_header hdr;
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/*[IN] ID of the client that wants to set the voltage */
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u8 client_id;
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/*
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* [IN] The list containing target voltage and
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* noise-unaware Vmin value for the VOLT_RAILs.
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*/
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struct ctrl_volt_volt_rail_list_v1 rail_list;
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u32 scratch[1];
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};
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/*
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* Defines the structure that holds data
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* used to execute VOLT_RAIL_GET_VOLTAGE RPC.
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*/
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struct nv_pmu_rpc_struct_volt_volt_rail_get_voltage {
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/*[IN/OUT] Must be first field in RPC structure */
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struct nv_pmu_rpc_header hdr;
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/* [OUT] Current voltage in uv */
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u32 voltage_uv;
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/* [IN] Voltage Rail Table Index */
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u8 rail_idx;
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u32 scratch[1];
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};
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#endif /* _GPMUIFVOLT_H_*/
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