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38ad90b484
JIRA DNVGPU-88 Change-Id: Idecfff5a80fadde77887385491dd6b73b1956bac Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1202551 (cherry picked from commit 3bcf9bad93fb6fdd4b87430b346ea41533149108) Reviewed-on: http://git-master/r/1223854 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
74 lines
1.6 KiB
C
74 lines
1.6 KiB
C
/*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef _GPMUIFSEQ_H_
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#define _GPMUIFSEQ_H_
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#include "gk20a/pmu_common.h"
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#define PMU_UNIT_SEQ (0x02)
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/*!
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* @file gpmuifseq.h
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* @brief PMU Command/Message Interfaces - Sequencer
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*/
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/*!
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* Defines the identifiers various high-level types of sequencer commands.
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*
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* _RUN_SCRIPT @ref NV_PMU_SEQ_CMD_RUN_SCRIPT
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*/
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enum {
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NV_PMU_SEQ_CMD_ID_RUN_SCRIPT = 0,
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};
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struct nv_pmu_seq_cmd_run_script {
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u8 cmd_type;
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u8 pad[3];
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struct pmu_allocation_v3 script_alloc;
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struct pmu_allocation_v3 reg_alloc;
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};
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#define NV_PMU_SEQ_CMD_ALLOC_OFFSET 4
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#define NV_PMU_SEQ_MSG_ALLOC_OFFSET \
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(NV_PMU_SEQ_CMD_ALLOC_OFFSET + NV_PMU_CMD_ALLOC_SIZE)
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struct nv_pmu_seq_cmd {
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struct pmu_hdr hdr;
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union {
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u8 cmd_type;
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struct nv_pmu_seq_cmd_run_script run_script;
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};
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};
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enum {
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NV_PMU_SEQ_MSG_ID_RUN_SCRIPT = 0,
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};
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struct nv_pmu_seq_msg_run_script {
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u8 msg_type;
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u8 error_code;
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u16 error_pc;
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u32 timeout_stat;
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};
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struct nv_pmu_seq_msg {
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struct pmu_hdr hdr;
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union {
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u8 msg_type;
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struct nv_pmu_seq_msg_run_script run_script;
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};
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};
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#endif
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