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983c15bca2
-Created ucode_perf_pstate_inf.h and moved all pstate interface structs and MACROs. -Created nvgpu_perf_pstate_get_lpwr_index for getting lpwr index -Created nvgpu_clk_domain_get_from_index for getting clk_domain from index -Removed pstate_get_status code which is not needed for tu10a profile -Removed MACROs and includes which are not needed NVGPU-4448 Change-Id: I516816a1d92a60a91ea479cb9c334d332d3d7a89 Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2264716 GVS: Gerrit_Virtual_Submit Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
46 lines
1.5 KiB
C
46 lines
1.5 KiB
C
/*
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* general p state infrastructure
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*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_PERF_PSTATE_H
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#define NVGPU_PERF_PSTATE_H
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#define CTRL_PERF_PSTATE_TYPE_35 0x05U
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struct clk_set_info_list {
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u32 num_info;
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struct clk_set_info clksetinfo[CLK_SET_INFO_MAX_SIZE];
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};
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struct pstate {
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struct boardobj super;
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u32 num;
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u8 lpwr_entry_idx;
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u32 flags;
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u8 pcie_idx;
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u8 nvlink_idx;
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struct clk_set_info_list clklist;
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};
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#endif /* NVGPU_PERF_PSTATE_H */
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