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dc82262b99
Move nvgpu_gr structure to private file gr_priv.h Include the private file where gr variables are used. JIRA NVGPU-3132 JIRA NVGPU-3079 Change-Id: Ib26ca5c5cb25fd8dd013a7c643278efc34aa55d4 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2098021 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
106 lines
2.7 KiB
C
106 lines
2.7 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GR_PRIV_H
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#define NVGPU_GR_PRIV_H
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#include <nvgpu/types.h>
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#include <nvgpu/cond.h>
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struct nvgpu_gr_ctx_desc;
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struct nvgpu_gr_global_ctx_buffer_desc;
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struct nvgpu_gr_obj_ctx_golden_image;
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struct nvgpu_gr_config;
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struct nvgpu_gr_zbc;
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struct nvgpu_gr_hwpm_map;
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struct nvgpu_gr_zcull;
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struct gk20a_cs_snapshot;
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struct gr_channel_map_tlb_entry {
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u32 curr_ctx;
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u32 chid;
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u32 tsgid;
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};
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struct nvgpu_gr {
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struct gk20a *g;
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struct {
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bool golden_image_initialized;
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u32 golden_image_size;
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u32 pm_ctxsw_image_size;
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u32 preempt_image_size;
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u32 zcull_image_size;
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} ctx_vars;
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struct nvgpu_mutex ctx_mutex; /* protect golden ctx init */
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struct nvgpu_cond init_wq;
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bool initialized;
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u32 num_fbps;
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u32 max_fbps_count;
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struct nvgpu_gr_global_ctx_buffer_desc *global_ctx_buffer;
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struct nvgpu_gr_obj_ctx_golden_image *golden_image;
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struct nvgpu_gr_ctx_desc *gr_ctx_desc;
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struct nvgpu_gr_config *config;
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struct nvgpu_gr_hwpm_map *hwpm_map;
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struct nvgpu_gr_zcull *zcull;
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struct nvgpu_gr_zbc *zbc;
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struct nvgpu_gr_falcon *falcon;
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#define GR_CHANNEL_MAP_TLB_SIZE 2U /* must of power of 2 */
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struct gr_channel_map_tlb_entry chid_tlb[GR_CHANNEL_MAP_TLB_SIZE];
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u32 channel_tlb_flush_index;
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struct nvgpu_spinlock ch_tlb_lock;
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void (*remove_support)(struct gk20a *g);
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bool sw_ready;
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u32 fecs_feature_override_ecc_val;
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u32 cilp_preempt_pending_chid;
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u32 fbp_en_mask;
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u32 *fbp_rop_l2_en_mask;
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#if defined(CONFIG_GK20A_CYCLE_STATS)
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struct nvgpu_mutex cs_lock;
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struct gk20a_cs_snapshot *cs_data;
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#endif
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u32 max_css_buffer_size;
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u32 max_ctxsw_ring_buffer_size;
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};
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#endif /* NVGPU_GR_PRIV_H */
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