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de6b40b862
MISRA rule 21.2 doesn't allow the use of macro names which start with an underscore. These leading underscores are to be removed from the macro names. This patch will fix such violations in ctrl by renaming them to follow the convention, 'NVGPU_PARENT-DIR_HEADER-NAME' when there is no keyword repetition between file name and directory or 'NVGPU_HEADER-NAME' when there is repetition. JIRA NVGPU-1028 Change-Id: Ia7e5bf76dd2a8689e365bdeb27eac4b6e9ca4cfd Signed-off-by: smadhavan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1815657 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
104 lines
3.1 KiB
C
104 lines
3.1 KiB
C
/*
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* general p state infrastructure
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*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_CTRLPERF_H
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#define NVGPU_CTRLPERF_H
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struct ctrl_perf_volt_rail_list_item {
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u8 volt_domain;
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u32 voltage_uv;
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u32 voltage_min_noise_unaware_uv;
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};
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struct ctrl_perf_volt_rail_list {
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u8 num_rails;
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struct ctrl_perf_volt_rail_list_item
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rails[CTRL_VOLT_VOLT_RAIL_MAX_RAILS];
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};
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union ctrl_perf_vfe_var_single_sensed_fuse_value_data {
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int signed_value;
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u32 unsigned_value;
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};
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struct ctrl_perf_vfe_var_single_sensed_fuse_value {
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bool b_signed;
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union ctrl_perf_vfe_var_single_sensed_fuse_value_data data;
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};
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struct ctrl_bios_vfield_register_segment_super {
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u8 low_bit;
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u8 high_bit;
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};
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struct ctrl_bios_vfield_register_segment_reg {
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struct ctrl_bios_vfield_register_segment_super super;
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u32 addr;
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};
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struct ctrl_bios_vfield_register_segment_index_reg {
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struct ctrl_bios_vfield_register_segment_super super;
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u32 addr;
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u32 reg_index;
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u32 index;
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};
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union ctrl_bios_vfield_register_segment_data {
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struct ctrl_bios_vfield_register_segment_reg reg;
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struct ctrl_bios_vfield_register_segment_index_reg index_reg;
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};
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struct ctrl_bios_vfield_register_segment {
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u8 type;
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union ctrl_bios_vfield_register_segment_data data;
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};
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#define NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX 1
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struct ctrl_perf_vfe_var_single_sensed_fuse_info {
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u8 segment_count;
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struct ctrl_bios_vfield_register_segment segments[NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX];
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};
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struct ctrl_perf_vfe_var_single_sensed_fuse_override_info {
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u32 fuse_val_override;
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u8 b_fuse_regkey_override;
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};
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struct ctrl_perf_vfe_var_single_sensed_fuse_vfield_info {
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struct ctrl_perf_vfe_var_single_sensed_fuse_info fuse;
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u32 fuse_val_default;
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u32 hw_correction_scale;
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int hw_correction_offset;
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u8 v_field_id;
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};
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struct ctrl_perf_vfe_var_single_sensed_fuse_ver_vfield_info {
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struct ctrl_perf_vfe_var_single_sensed_fuse_info fuse;
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u8 ver_expected;
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bool b_ver_check;
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bool b_use_default_on_ver_check_fail;
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u8 v_field_id_ver;
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};
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#endif /* NVGPU_CTRLPERF_H */
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