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git://nv-tegra.nvidia.com/linux-nvgpu.git
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df87591b7d
1) Added multi gr handling for dbg_ioctl apis. 2) Added nvgpu_assert() in gr_instances.h (for legacy mode). 3) Added multi gr handling for prof_ioctl apis. 4) Added multi gr handling for profiler. 5) Added multi gr handling for ctxsw enable/disable apis. 6) Updated update_hwpm_ctxsw_mode() HAL for multi gr handling. JIRA NVGPU-5656 Change-Id: I3024d5e6d39bba7a1ae54c5e88c061ce9133e710 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2538761 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com> Reviewed-by: Dinesh T <dt@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
126 lines
3.7 KiB
C
126 lines
3.7 KiB
C
/*
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* Tegra GK20A GPU Debugger Driver
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*
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* Copyright (c) 2013-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_DEBUGGER_H
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#define NVGPU_DEBUGGER_H
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#ifdef CONFIG_NVGPU_DEBUGGER
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#include <nvgpu/cond.h>
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#include <nvgpu/lock.h>
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#include <nvgpu/list.h>
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struct gk20a;
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struct nvgpu_channel;
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struct dbg_session_gk20a;
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struct nvgpu_profiler_object;
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struct nvgpu_channel *
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nvgpu_dbg_gpu_get_session_channel(struct dbg_session_gk20a *dbg_s);
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struct dbg_gpu_session_events {
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struct nvgpu_cond wait_queue;
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bool events_enabled;
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int num_pending_events;
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};
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struct dbg_session_gk20a {
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/* dbg session id used for trace/prints */
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int id;
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/* profiler session, if any */
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bool is_profiler;
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/* power enabled or disabled */
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bool is_pg_disabled;
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/* timeouts enabled or disabled */
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bool is_timeout_disabled;
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struct gk20a *g;
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/* list of bound channels, if any */
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struct nvgpu_list_node ch_list;
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struct nvgpu_mutex ch_list_lock;
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/* event support */
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struct dbg_gpu_session_events dbg_events;
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bool broadcast_stop_trigger;
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struct nvgpu_mutex ioctl_lock;
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/*
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* Dummy profiler object for debug session to synchronize PMA
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* reservation and HWPM system reset with new context/device
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* profilers.
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*/
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struct nvgpu_profiler_object *prof;
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/** GPU instance Id */
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u32 gpu_instance_id;
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};
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struct dbg_session_data {
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struct dbg_session_gk20a *dbg_s;
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struct nvgpu_list_node dbg_s_entry;
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};
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static inline struct dbg_session_data *
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dbg_session_data_from_dbg_s_entry(struct nvgpu_list_node *node)
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{
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return (struct dbg_session_data *)
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((uintptr_t)node - offsetof(struct dbg_session_data, dbg_s_entry));
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};
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struct dbg_session_channel_data {
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int channel_fd;
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u32 chid;
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struct nvgpu_list_node ch_entry;
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struct dbg_session_data *session_data;
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int (*unbind_single_channel)(struct dbg_session_gk20a *dbg_s,
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struct dbg_session_channel_data *ch_data);
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};
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static inline struct dbg_session_channel_data *
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dbg_session_channel_data_from_ch_entry(struct nvgpu_list_node *node)
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{
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return (struct dbg_session_channel_data *)
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((uintptr_t)node - offsetof(struct dbg_session_channel_data, ch_entry));
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};
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/* used by the interrupt handler to post events */
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void nvgpu_dbg_gpu_post_events(struct nvgpu_channel *ch);
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bool nvgpu_dbg_gpu_broadcast_stop_trigger(struct nvgpu_channel *ch);
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void nvgpu_dbg_gpu_clear_broadcast_stop_trigger(struct nvgpu_channel *ch);
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int nvgpu_dbg_set_powergate(struct dbg_session_gk20a *dbg_s, bool disable_powergate);
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void nvgpu_dbg_session_post_event(struct dbg_session_gk20a *dbg_s);
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u32 nvgpu_set_powergate_locked(struct dbg_session_gk20a *dbg_s,
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bool mode);
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#endif /* CONFIG_NVGPU_DEBUGGER */
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#endif /* NVGPU_DEBUGGER_H */
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