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e852ea6f2a
Use correct header files guard for gr_falcon_priv.h JIRA NVGPU-3226 Change-Id: Ibdea01ba697017b70c23e0245ba7f9dbe33d7dac Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2110735 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
130 lines
3.5 KiB
C
130 lines
3.5 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef GR_FALCON_PRIV_H
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#define GR_FALCON_PRIV_H
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#include <nvgpu/types.h>
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#include <nvgpu/nvgpu_mem.h>
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struct nvgpu_ctxsw_ucode_segments;
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struct nvgpu_fecs_method_op {
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struct {
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u32 addr;
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u32 data;
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} method;
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struct {
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u32 id;
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u32 data;
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u32 clr;
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u32 *ret;
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u32 ok;
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u32 fail;
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} mailbox;
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struct {
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u32 ok;
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u32 fail;
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} cond;
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};
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struct nvgpu_ctxsw_bootloader_desc {
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u32 start_offset;
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u32 size;
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u32 imem_offset;
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u32 entry_point;
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};
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struct nvgpu_ctxsw_ucode_info {
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u64 *p_va;
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struct nvgpu_mem inst_blk_desc;
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struct nvgpu_mem surface_desc;
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struct nvgpu_ctxsw_ucode_segments fecs;
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struct nvgpu_ctxsw_ucode_segments gpccs;
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};
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struct nvgpu_gr_falcon_query_sizes {
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u32 golden_image_size;
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u32 pm_ctxsw_image_size;
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u32 preempt_image_size;
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u32 zcull_image_size;
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};
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struct nvgpu_gr_falcon {
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struct nvgpu_ctxsw_ucode_info ctxsw_ucode_info;
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struct nvgpu_mutex fecs_mutex; /* protect fecs method */
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bool skip_ucode_init;
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struct nvgpu_gr_falcon_query_sizes sizes;
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};
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enum wait_ucode_status {
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WAIT_UCODE_LOOP,
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WAIT_UCODE_TIMEOUT,
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WAIT_UCODE_ERROR,
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WAIT_UCODE_OK
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};
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enum {
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GR_IS_UCODE_OP_EQUAL,
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GR_IS_UCODE_OP_NOT_EQUAL,
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GR_IS_UCODE_OP_AND,
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GR_IS_UCODE_OP_LESSER,
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GR_IS_UCODE_OP_LESSER_EQUAL,
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GR_IS_UCODE_OP_SKIP
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};
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enum {
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eUcodeHandshakeInitComplete = 1,
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eUcodeHandshakeMethodFinished
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};
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/* sums over the ucode files as sequences of u32, computed to the
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* boot_signature field in the structure above */
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/* T18X FECS remains same as T21X,
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* so FALCON_UCODE_SIG_T21X_FECS_WITH_RESERVED used
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* for T18X*/
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#define FALCON_UCODE_SIG_T18X_GPCCS_WITH_RESERVED 0x68edab34U
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#define FALCON_UCODE_SIG_T21X_FECS_WITH_DMEM_SIZE 0x9121ab5cU
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#define FALCON_UCODE_SIG_T21X_FECS_WITH_RESERVED 0x9125ab5cU
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#define FALCON_UCODE_SIG_T12X_FECS_WITH_RESERVED 0x8a621f78U
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#define FALCON_UCODE_SIG_T12X_FECS_WITHOUT_RESERVED 0x67e5344bU
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#define FALCON_UCODE_SIG_T12X_FECS_OLDER 0x56da09fU
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#define FALCON_UCODE_SIG_T21X_GPCCS_WITH_RESERVED 0x3d3d65e2U
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#define FALCON_UCODE_SIG_T12X_GPCCS_WITH_RESERVED 0x303465d5U
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#define FALCON_UCODE_SIG_T12X_GPCCS_WITHOUT_RESERVED 0x3fdd33d3U
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#define FALCON_UCODE_SIG_T12X_GPCCS_OLDER 0x53d7877U
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#define FALCON_UCODE_SIG_T21X_FECS_WITHOUT_RESERVED 0x93671b7dU
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#define FALCON_UCODE_SIG_T21X_FECS_WITHOUT_RESERVED2 0x4d6cbc10U
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#define FALCON_UCODE_SIG_T21X_GPCCS_WITHOUT_RESERVED 0x393161daU
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#endif /* GR_FALCON_PRIV_H */
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