mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-22 09:12:24 +03:00
e0a1fcf5f5
Add a new Central Interrupt Controller(CIC) unit in common code.
The interrupt handling is done in a distributed manner currently.
The error handling policy for different errors resides in each unit's
ISR code. The goal is to converge this data under one central place -
the CIC unit.
This patch creates framework for CIC unit and moves the gv11b QNX
safety LUT to CIC unit. All the error reporting APIs from different
units are also moved to CIC.
New APIs are exposed by CIC unit to access its internal data like:
1. Struct err_desc - the static err handling /injection data per
error id
2. Num_hw_modules - the number of error reporting HW units
supported by CIC
Init and deinit of CIC unit:
1. CIC unit should be initialized earlyon during boot so that it
is available for any interrupt handling.
2. Initialize CIC just before the interrupts are enabled during
boot.
3. Similarly, CIC is disabled late during deinit cycle; right
after the interrupts are masked.
LUT:
1. LUT is currently used only for reporting error to safety
services in gv11b QNX safety build.
2. This error handling policy LUT currently has only two levels
of handing - correctable and quiecse.
3. Once, the error handling policy decision is moved from leaf
unit nodes to CIC, LUT will be updated to have additional levels
like fast recovery and full recovery.
4. Also, then a separate LUT will be added for each platform/build.
5. In current framework, the LUT is set to NULL for all
configurations except gv11b.
report_err() ops is added to report error to safety services.
This ops is only effective for gv11b qnx build; and set to NULL for
other configurations.
NVGPU-6521
NVGPU-6523
NVGPU-6750
NVGPU-6758
NVGPU-6760
NVGPU-6754
Change-Id: I24be7836a96d787741e37b732e19863ed8014635
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2518683
Reviewed-by: Ajesh K V <akv@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
92 lines
3.0 KiB
C
92 lines
3.0 KiB
C
/*
|
|
* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
|
|
*
|
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
* copy of this software and associated documentation files (the "Software"),
|
|
* to deal in the Software without restriction, including without limitation
|
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
* and/or sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following conditions:
|
|
*
|
|
* The above copyright notice and this permission notice shall be included in
|
|
* all copies or substantial portions of the Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
|
* DEALINGS IN THE SOFTWARE.
|
|
*/
|
|
|
|
#include <nvgpu/gk20a.h>
|
|
#include <nvgpu/nvgpu_init.h>
|
|
#include <nvgpu/nvgpu_err.h>
|
|
#include <nvgpu/nvgpu_err_info.h>
|
|
#include <nvgpu/cic.h>
|
|
|
|
#include "cic_priv.h"
|
|
|
|
void nvgpu_report_ce_err(struct gk20a *g, u32 hw_unit,
|
|
u32 inst, u32 err_id, u32 intr_info)
|
|
{
|
|
int err = 0;
|
|
struct nvgpu_err_desc *err_desc = NULL;
|
|
struct nvgpu_err_msg err_pkt;
|
|
|
|
if (g->ops.cic.report_err == NULL) {
|
|
cic_dbg(g, "CIC does not support reporting error "
|
|
"to safety services");
|
|
return;
|
|
}
|
|
|
|
if (hw_unit != NVGPU_ERR_MODULE_CE) {
|
|
nvgpu_err(g, "invalid hw module (%u)", hw_unit);
|
|
err = -EINVAL;
|
|
goto handle_report_failure;
|
|
}
|
|
|
|
err = nvgpu_cic_get_err_desc(g, hw_unit, err_id, &err_desc);
|
|
if (err != 0) {
|
|
nvgpu_err(g, "Failed to get err_desc for "
|
|
"err_id (%u) for hw module (%u)",
|
|
err_id, hw_unit);
|
|
goto handle_report_failure;
|
|
}
|
|
|
|
nvgpu_init_ce_err_msg(&err_pkt);
|
|
err_pkt.hw_unit_id = hw_unit;
|
|
err_pkt.err_id = err_desc->error_id;
|
|
err_pkt.is_critical = err_desc->is_critical;
|
|
err_pkt.err_info.ce_info.header.sub_unit_id = inst;
|
|
err_pkt.err_desc = err_desc;
|
|
/* sub_err_type can be decoded using intr_info by referring
|
|
* to the interrupt status register definition corresponding
|
|
* to the error that is being reported.
|
|
*/
|
|
err_pkt.err_info.ce_info.header.sub_err_type = intr_info;
|
|
err_pkt.err_size = nvgpu_safe_cast_u64_to_u8(
|
|
sizeof(err_pkt.err_info.ce_info));
|
|
|
|
if (g->ops.cic.report_err != NULL) {
|
|
err = g->ops.cic.report_err(g, (void *)&err_pkt,
|
|
sizeof(err_pkt), err_desc->is_critical);
|
|
if (err != 0) {
|
|
nvgpu_err(g, "Failed to report CE error: "
|
|
"inst=%u err_id=%u intr_info=%u",
|
|
inst, err_id, intr_info);
|
|
}
|
|
}
|
|
handle_report_failure:
|
|
if (err != 0) {
|
|
nvgpu_sw_quiesce(g);
|
|
}
|
|
}
|
|
|
|
void nvgpu_inject_ce_swerror(struct gk20a *g, u32 hw_unit,
|
|
u32 err_index, u32 sub_err_type)
|
|
{
|
|
nvgpu_report_ce_err(g, hw_unit, 0U, err_index, sub_err_type);
|
|
}
|