mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-23 01:50:07 +03:00
0ffc5fa5e4
Add BLCG and SLCG clock gating support for HSHUB unit on gv11b
Register list for BLCG and SLCG is auto generated with scripts.
Add HAL operations to enable/disable HSHUB clock gating
Re-generate gv11b reglist so that all the manually commented registers
are automatically deleted. Some of the unicast registers are also
deleted. We already have corresponding broadcast registers present.
Cherry-pick/manually port from dev-main
Bug 2526212
Change-Id: I2654f158daa802bcf992e103ed4a44675aa5fd4d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2150199
(cherry picked from commit e34b6f76d3)
Reviewed-on: https://git-master.nvidia.com/r/2224708
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-by: Luis Dib <ldib@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
629 lines
16 KiB
C
629 lines
16 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/enabled.h>
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#include <nvgpu/power_features/cg.h>
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static void nvgpu_cg_set_mode(struct gk20a *g, int cgmode, int mode_config)
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{
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u32 engine_idx;
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u32 active_engine_id = 0;
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struct fifo_engine_info_gk20a *engine_info = NULL;
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struct fifo_gk20a *f = &g->fifo;
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nvgpu_log_fn(g, " ");
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for (engine_idx = 0; engine_idx < f->num_engines; ++engine_idx) {
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active_engine_id = f->active_engines_list[engine_idx];
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engine_info = &f->engine_info[active_engine_id];
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/* gr_engine supports both BLCG and ELCG */
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if ((cgmode == BLCG_MODE) && (engine_info->engine_enum ==
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ENGINE_GR_GK20A)) {
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g->ops.therm.init_blcg_mode(g, (u32)mode_config,
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active_engine_id);
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break;
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} else if (cgmode == ELCG_MODE) {
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g->ops.therm.init_elcg_mode(g, (u32)mode_config,
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active_engine_id);
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} else {
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nvgpu_err(g, "invalid cg mode %d, config %d for "
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"act_eng_id %d",
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cgmode, mode_config, active_engine_id);
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}
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}
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}
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void nvgpu_cg_elcg_enable_no_wait(struct gk20a *g)
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{
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nvgpu_log_fn(g, " ");
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if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_ELCG)) {
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return;
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}
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nvgpu_mutex_acquire(&g->cg_pg_lock);
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if (g->elcg_enabled) {
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nvgpu_cg_set_mode(g, ELCG_MODE, ELCG_AUTO);
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}
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nvgpu_mutex_release(&g->cg_pg_lock);
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}
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void nvgpu_cg_elcg_disable_no_wait(struct gk20a *g)
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{
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nvgpu_log_fn(g, " ");
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if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_ELCG)) {
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return;
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}
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nvgpu_mutex_acquire(&g->cg_pg_lock);
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if (g->elcg_enabled) {
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nvgpu_cg_set_mode(g, ELCG_MODE, ELCG_RUN);
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}
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nvgpu_mutex_release(&g->cg_pg_lock);
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}
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void nvgpu_cg_elcg_enable(struct gk20a *g)
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{
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nvgpu_log_fn(g, " ");
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if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_ELCG)) {
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return;
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}
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gk20a_gr_wait_initialized(g);
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nvgpu_mutex_acquire(&g->cg_pg_lock);
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if (g->elcg_enabled) {
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nvgpu_cg_set_mode(g, ELCG_MODE, ELCG_AUTO);
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}
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nvgpu_mutex_release(&g->cg_pg_lock);
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}
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void nvgpu_cg_elcg_disable(struct gk20a *g)
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{
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nvgpu_log_fn(g, " ");
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if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_ELCG)) {
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return;
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}
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gk20a_gr_wait_initialized(g);
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nvgpu_mutex_acquire(&g->cg_pg_lock);
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if (g->elcg_enabled) {
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nvgpu_cg_set_mode(g, ELCG_MODE, ELCG_RUN);
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}
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nvgpu_mutex_release(&g->cg_pg_lock);
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}
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void nvgpu_cg_blcg_mode_enable(struct gk20a *g)
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{
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nvgpu_log_fn(g, " ");
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if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
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return;
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}
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gk20a_gr_wait_initialized(g);
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nvgpu_mutex_acquire(&g->cg_pg_lock);
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if (g->blcg_enabled) {
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nvgpu_cg_set_mode(g, BLCG_MODE, BLCG_AUTO);
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}
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nvgpu_mutex_release(&g->cg_pg_lock);
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}
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void nvgpu_cg_blcg_mode_disable(struct gk20a *g)
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{
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nvgpu_log_fn(g, " ");
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if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
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return;
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}
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gk20a_gr_wait_initialized(g);
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nvgpu_mutex_acquire(&g->cg_pg_lock);
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if (g->blcg_enabled) {
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nvgpu_cg_set_mode(g, BLCG_MODE, BLCG_RUN);
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}
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nvgpu_mutex_release(&g->cg_pg_lock);
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}
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void nvgpu_cg_blcg_fb_ltc_load_enable(struct gk20a *g)
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{
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nvgpu_log_fn(g, " ");
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if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
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return;
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}
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nvgpu_mutex_acquire(&g->cg_pg_lock);
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if (!g->blcg_enabled) {
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goto done;
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}
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if (g->ops.clock_gating.blcg_fb_load_gating_prod != NULL) {
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g->ops.clock_gating.blcg_fb_load_gating_prod(g, true);
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}
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if (g->ops.clock_gating.blcg_ltc_load_gating_prod != NULL) {
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g->ops.clock_gating.blcg_ltc_load_gating_prod(g, true);
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}
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done:
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nvgpu_mutex_release(&g->cg_pg_lock);
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}
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void nvgpu_cg_blcg_fifo_load_enable(struct gk20a *g)
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{
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nvgpu_log_fn(g, " ");
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if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
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return;
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}
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nvgpu_mutex_acquire(&g->cg_pg_lock);
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if (!g->blcg_enabled) {
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goto done;
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}
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if (g->ops.clock_gating.blcg_fifo_load_gating_prod != NULL) {
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g->ops.clock_gating.blcg_fifo_load_gating_prod(g, true);
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}
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done:
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nvgpu_mutex_release(&g->cg_pg_lock);
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}
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void nvgpu_cg_blcg_pmu_load_enable(struct gk20a *g)
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{
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nvgpu_log_fn(g, " ");
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if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
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return;
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}
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nvgpu_mutex_acquire(&g->cg_pg_lock);
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if (!g->blcg_enabled) {
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goto done;
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}
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if (g->ops.clock_gating.blcg_pmu_load_gating_prod != NULL) {
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g->ops.clock_gating.blcg_pmu_load_gating_prod(g, true);
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}
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done:
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nvgpu_mutex_release(&g->cg_pg_lock);
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}
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void nvgpu_cg_blcg_ce_load_enable(struct gk20a *g)
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{
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nvgpu_log_fn(g, " ");
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if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
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return;
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}
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nvgpu_mutex_acquire(&g->cg_pg_lock);
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if (!g->blcg_enabled) {
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goto done;
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}
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if (g->ops.clock_gating.blcg_ce_load_gating_prod != NULL) {
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g->ops.clock_gating.blcg_ce_load_gating_prod(g, true);
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}
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done:
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nvgpu_mutex_release(&g->cg_pg_lock);
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}
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void nvgpu_cg_blcg_gr_load_enable(struct gk20a *g)
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{
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nvgpu_log_fn(g, " ");
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if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
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return;
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}
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nvgpu_mutex_acquire(&g->cg_pg_lock);
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if (!g->blcg_enabled) {
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goto done;
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}
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if (g->ops.clock_gating.blcg_gr_load_gating_prod != NULL) {
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g->ops.clock_gating.blcg_gr_load_gating_prod(g, true);
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}
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done:
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nvgpu_mutex_release(&g->cg_pg_lock);
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}
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void nvgpu_cg_slcg_fb_ltc_load_enable(struct gk20a *g)
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{
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nvgpu_log_fn(g, " ");
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if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
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return;
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}
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nvgpu_mutex_acquire(&g->cg_pg_lock);
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if (!g->slcg_enabled) {
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goto done;
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}
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if (g->ops.clock_gating.slcg_fb_load_gating_prod != NULL) {
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g->ops.clock_gating.slcg_fb_load_gating_prod(g, true);
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}
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if (g->ops.clock_gating.slcg_ltc_load_gating_prod != NULL) {
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g->ops.clock_gating.slcg_ltc_load_gating_prod(g, true);
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}
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done:
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nvgpu_mutex_release(&g->cg_pg_lock);
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}
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void nvgpu_cg_slcg_priring_load_enable(struct gk20a *g)
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{
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nvgpu_log_fn(g, " ");
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if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
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return;
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}
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nvgpu_mutex_acquire(&g->cg_pg_lock);
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if (!g->slcg_enabled) {
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goto done;
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}
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if (g->ops.clock_gating.slcg_priring_load_gating_prod != NULL) {
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g->ops.clock_gating.slcg_priring_load_gating_prod(g, true);
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}
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done:
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nvgpu_mutex_release(&g->cg_pg_lock);
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}
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void nvgpu_cg_slcg_gr_perf_ltc_load_enable(struct gk20a *g)
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{
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nvgpu_log_fn(g, " ");
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if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
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return;
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}
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gk20a_gr_wait_initialized(g);
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nvgpu_mutex_acquire(&g->cg_pg_lock);
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if (!g->slcg_enabled) {
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goto done;
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}
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if (g->ops.clock_gating.slcg_ltc_load_gating_prod != NULL) {
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g->ops.clock_gating.slcg_ltc_load_gating_prod(g, true);
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}
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if (g->ops.clock_gating.slcg_perf_load_gating_prod != NULL) {
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g->ops.clock_gating.slcg_perf_load_gating_prod(g, true);
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}
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if (g->ops.clock_gating.slcg_gr_load_gating_prod != NULL) {
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g->ops.clock_gating.slcg_gr_load_gating_prod(g, true);
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}
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done:
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nvgpu_mutex_release(&g->cg_pg_lock);
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}
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void nvgpu_cg_slcg_gr_perf_ltc_load_disable(struct gk20a *g)
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{
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nvgpu_log_fn(g, " ");
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if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
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return;
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}
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gk20a_gr_wait_initialized(g);
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nvgpu_mutex_acquire(&g->cg_pg_lock);
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if (!g->slcg_enabled) {
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goto done;
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}
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if (g->ops.clock_gating.slcg_gr_load_gating_prod != NULL) {
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g->ops.clock_gating.slcg_gr_load_gating_prod(g, false);
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}
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if (g->ops.clock_gating.slcg_perf_load_gating_prod != NULL) {
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g->ops.clock_gating.slcg_perf_load_gating_prod(g, false);
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}
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if (g->ops.clock_gating.slcg_ltc_load_gating_prod != NULL) {
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g->ops.clock_gating.slcg_ltc_load_gating_prod(g, false);
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}
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done:
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nvgpu_mutex_release(&g->cg_pg_lock);
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}
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void nvgpu_cg_slcg_fifo_load_enable(struct gk20a *g)
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{
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nvgpu_log_fn(g, " ");
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if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
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return;
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}
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nvgpu_mutex_acquire(&g->cg_pg_lock);
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if (!g->slcg_enabled) {
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goto done;
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}
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if (g->ops.clock_gating.slcg_fifo_load_gating_prod != NULL) {
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g->ops.clock_gating.slcg_fifo_load_gating_prod(g, true);
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}
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done:
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nvgpu_mutex_release(&g->cg_pg_lock);
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}
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void nvgpu_cg_slcg_pmu_load_enable(struct gk20a *g)
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{
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nvgpu_log_fn(g, " ");
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if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
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return;
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}
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nvgpu_mutex_acquire(&g->cg_pg_lock);
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if (!g->slcg_enabled) {
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goto done;
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}
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if (g->ops.clock_gating.slcg_pmu_load_gating_prod != NULL) {
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g->ops.clock_gating.slcg_pmu_load_gating_prod(g, true);
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}
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done:
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nvgpu_mutex_release(&g->cg_pg_lock);
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}
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void nvgpu_cg_slcg_ce2_load_enable(struct gk20a *g)
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{
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nvgpu_log_fn(g, " ");
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if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
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return;
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}
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nvgpu_mutex_acquire(&g->cg_pg_lock);
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if (!g->slcg_enabled) {
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goto done;
|
|
}
|
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if (g->ops.clock_gating.slcg_ce2_load_gating_prod != NULL) {
|
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g->ops.clock_gating.slcg_ce2_load_gating_prod(g, true);
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}
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done:
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nvgpu_mutex_release(&g->cg_pg_lock);
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}
|
|
|
|
void nvgpu_cg_init_gr_load_gating_prod(struct gk20a *g)
|
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{
|
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nvgpu_log_fn(g, " ");
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nvgpu_mutex_acquire(&g->cg_pg_lock);
|
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|
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if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
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goto check_can_blcg;
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}
|
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if (!g->slcg_enabled) {
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goto check_can_blcg;
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|
}
|
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|
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if (g->ops.clock_gating.slcg_bus_load_gating_prod != NULL) {
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g->ops.clock_gating.slcg_bus_load_gating_prod(g, true);
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}
|
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if (g->ops.clock_gating.slcg_chiplet_load_gating_prod != NULL) {
|
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g->ops.clock_gating.slcg_chiplet_load_gating_prod(g, true);
|
|
}
|
|
if (g->ops.clock_gating.slcg_gr_load_gating_prod != NULL) {
|
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g->ops.clock_gating.slcg_gr_load_gating_prod(g, true);
|
|
}
|
|
if (g->ops.clock_gating.slcg_ctxsw_firmware_load_gating_prod != NULL) {
|
|
g->ops.clock_gating.slcg_ctxsw_firmware_load_gating_prod(g,
|
|
true);
|
|
}
|
|
if (g->ops.clock_gating.slcg_perf_load_gating_prod != NULL) {
|
|
g->ops.clock_gating.slcg_perf_load_gating_prod(g, true);
|
|
}
|
|
if (g->ops.clock_gating.slcg_xbar_load_gating_prod != NULL) {
|
|
g->ops.clock_gating.slcg_xbar_load_gating_prod(g, true);
|
|
}
|
|
if (g->ops.clock_gating.slcg_hshub_load_gating_prod != NULL) {
|
|
g->ops.clock_gating.slcg_hshub_load_gating_prod(g, true);
|
|
}
|
|
|
|
check_can_blcg:
|
|
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
|
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goto pg_gr_load;
|
|
}
|
|
if (!g->blcg_enabled) {
|
|
goto pg_gr_load;
|
|
}
|
|
if (g->ops.clock_gating.blcg_bus_load_gating_prod != NULL) {
|
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g->ops.clock_gating.blcg_bus_load_gating_prod(g, true);
|
|
}
|
|
if (g->ops.clock_gating.blcg_gr_load_gating_prod != NULL) {
|
|
g->ops.clock_gating.blcg_gr_load_gating_prod(g, true);
|
|
}
|
|
if (g->ops.clock_gating.blcg_ctxsw_firmware_load_gating_prod != NULL) {
|
|
g->ops.clock_gating.blcg_ctxsw_firmware_load_gating_prod(g,
|
|
true);
|
|
}
|
|
if (g->ops.clock_gating.blcg_xbar_load_gating_prod != NULL) {
|
|
g->ops.clock_gating.blcg_xbar_load_gating_prod(g, true);
|
|
}
|
|
if (g->ops.clock_gating.blcg_hshub_load_gating_prod != NULL) {
|
|
g->ops.clock_gating.blcg_hshub_load_gating_prod(g, true);
|
|
}
|
|
pg_gr_load:
|
|
if (g->ops.clock_gating.pg_gr_load_gating_prod != NULL) {
|
|
g->ops.clock_gating.pg_gr_load_gating_prod(g, true);
|
|
}
|
|
|
|
nvgpu_mutex_release(&g->cg_pg_lock);
|
|
}
|
|
|
|
void nvgpu_cg_elcg_set_elcg_enabled(struct gk20a *g, bool enable)
|
|
{
|
|
nvgpu_log_fn(g, " ");
|
|
|
|
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_ELCG)) {
|
|
return;
|
|
}
|
|
|
|
gk20a_gr_wait_initialized(g);
|
|
|
|
nvgpu_mutex_release(&g->cg_pg_lock);
|
|
if (enable) {
|
|
if (!g->elcg_enabled) {
|
|
g->elcg_enabled = true;
|
|
nvgpu_cg_set_mode(g, ELCG_MODE, ELCG_AUTO);
|
|
}
|
|
} else {
|
|
if (g->elcg_enabled) {
|
|
g->elcg_enabled = false;
|
|
nvgpu_cg_set_mode(g, ELCG_MODE, ELCG_RUN);
|
|
}
|
|
}
|
|
nvgpu_mutex_release(&g->cg_pg_lock);
|
|
}
|
|
|
|
void nvgpu_cg_blcg_set_blcg_enabled(struct gk20a *g, bool enable)
|
|
{
|
|
bool load = false;
|
|
|
|
nvgpu_log_fn(g, " ");
|
|
|
|
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
|
|
return;
|
|
}
|
|
|
|
gk20a_gr_wait_initialized(g);
|
|
|
|
nvgpu_mutex_acquire(&g->cg_pg_lock);
|
|
if (enable) {
|
|
if (!g->blcg_enabled) {
|
|
load = true;
|
|
g->blcg_enabled = true;
|
|
}
|
|
} else {
|
|
if (g->blcg_enabled) {
|
|
load = true;
|
|
g->blcg_enabled = false;
|
|
}
|
|
}
|
|
if (!load ) {
|
|
goto done;
|
|
}
|
|
|
|
if (g->ops.clock_gating.blcg_bus_load_gating_prod != NULL) {
|
|
g->ops.clock_gating.blcg_bus_load_gating_prod(g, enable);
|
|
}
|
|
if (g->ops.clock_gating.blcg_ce_load_gating_prod != NULL) {
|
|
g->ops.clock_gating.blcg_ce_load_gating_prod(g, enable);
|
|
}
|
|
if (g->ops.clock_gating.blcg_ctxsw_firmware_load_gating_prod != NULL) {
|
|
g->ops.clock_gating.blcg_ctxsw_firmware_load_gating_prod(g,
|
|
enable);
|
|
}
|
|
if (g->ops.clock_gating.blcg_fb_load_gating_prod != NULL) {
|
|
g->ops.clock_gating.blcg_fb_load_gating_prod(g, enable);
|
|
}
|
|
if (g->ops.clock_gating.blcg_fifo_load_gating_prod != NULL) {
|
|
g->ops.clock_gating.blcg_fifo_load_gating_prod(g, enable);
|
|
}
|
|
if (g->ops.clock_gating.blcg_gr_load_gating_prod != NULL) {
|
|
g->ops.clock_gating.blcg_gr_load_gating_prod(g, enable);
|
|
}
|
|
if (g->ops.clock_gating.blcg_ltc_load_gating_prod != NULL) {
|
|
g->ops.clock_gating.blcg_ltc_load_gating_prod(g, enable);
|
|
}
|
|
if (g->ops.clock_gating.blcg_pmu_load_gating_prod != NULL) {
|
|
g->ops.clock_gating.blcg_pmu_load_gating_prod(g, enable);
|
|
}
|
|
if (g->ops.clock_gating.blcg_xbar_load_gating_prod != NULL) {
|
|
g->ops.clock_gating.blcg_xbar_load_gating_prod(g, enable);
|
|
}
|
|
if (g->ops.clock_gating.blcg_hshub_load_gating_prod != NULL) {
|
|
g->ops.clock_gating.blcg_hshub_load_gating_prod(g, enable);
|
|
}
|
|
|
|
done:
|
|
nvgpu_mutex_release(&g->cg_pg_lock);
|
|
}
|
|
|
|
void nvgpu_cg_slcg_set_slcg_enabled(struct gk20a *g, bool enable)
|
|
{
|
|
bool load = false;
|
|
|
|
nvgpu_log_fn(g, " ");
|
|
|
|
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
|
|
return;
|
|
}
|
|
|
|
gk20a_gr_wait_initialized(g);
|
|
|
|
nvgpu_mutex_acquire(&g->cg_pg_lock);
|
|
if (enable) {
|
|
if (!g->slcg_enabled) {
|
|
load = true;
|
|
g->slcg_enabled = true;
|
|
}
|
|
} else {
|
|
if (g->slcg_enabled) {
|
|
load = true;
|
|
g->slcg_enabled = false;
|
|
}
|
|
}
|
|
if (!load ) {
|
|
goto done;
|
|
}
|
|
|
|
if (g->ops.clock_gating.slcg_bus_load_gating_prod != NULL) {
|
|
g->ops.clock_gating.slcg_bus_load_gating_prod(g, enable);
|
|
}
|
|
if (g->ops.clock_gating.slcg_ce2_load_gating_prod != NULL) {
|
|
g->ops.clock_gating.slcg_ce2_load_gating_prod(g, enable);
|
|
}
|
|
if (g->ops.clock_gating.slcg_chiplet_load_gating_prod != NULL) {
|
|
g->ops.clock_gating.slcg_chiplet_load_gating_prod(g, enable);
|
|
}
|
|
if (g->ops.clock_gating.slcg_ctxsw_firmware_load_gating_prod !=
|
|
NULL) {
|
|
g->ops.clock_gating.slcg_ctxsw_firmware_load_gating_prod(g,
|
|
enable);
|
|
}
|
|
if (g->ops.clock_gating.slcg_fb_load_gating_prod != NULL) {
|
|
g->ops.clock_gating.slcg_fb_load_gating_prod(g, enable);
|
|
}
|
|
if (g->ops.clock_gating.slcg_fifo_load_gating_prod != NULL) {
|
|
g->ops.clock_gating.slcg_fifo_load_gating_prod(g, enable);
|
|
}
|
|
if (g->ops.clock_gating.slcg_gr_load_gating_prod != NULL) {
|
|
g->ops.clock_gating.slcg_gr_load_gating_prod(g, enable);
|
|
}
|
|
if (g->ops.clock_gating.slcg_ltc_load_gating_prod != NULL) {
|
|
g->ops.clock_gating.slcg_ltc_load_gating_prod(g, enable);
|
|
}
|
|
if (g->ops.clock_gating.slcg_perf_load_gating_prod != NULL) {
|
|
g->ops.clock_gating.slcg_perf_load_gating_prod(g, enable);
|
|
}
|
|
if (g->ops.clock_gating.slcg_priring_load_gating_prod != NULL) {
|
|
g->ops.clock_gating.slcg_priring_load_gating_prod(g,
|
|
enable);
|
|
}
|
|
if (g->ops.clock_gating.slcg_pmu_load_gating_prod != NULL) {
|
|
g->ops.clock_gating.slcg_pmu_load_gating_prod(g, enable);
|
|
}
|
|
if (g->ops.clock_gating.slcg_xbar_load_gating_prod != NULL) {
|
|
g->ops.clock_gating.slcg_xbar_load_gating_prod(g, enable);
|
|
}
|
|
if (g->ops.clock_gating.slcg_hshub_load_gating_prod != NULL) {
|
|
g->ops.clock_gating.slcg_hshub_load_gating_prod(g, enable);
|
|
}
|
|
|
|
done:
|
|
nvgpu_mutex_release(&g->cg_pg_lock);
|
|
}
|