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863b470644
-Moved PMU RTOS init & start RTOS from acr_gm20b.c file pmu.c method nvgpu_init_pmu_support() -Modified nvgpu_init_pmu_support() to init required interface for PMU RTOS & does start PMU RTOS in secure & non-secure based on NVGPU_SEC_PRIVSECURITY flag. -Created secured_pmu_start ops under PMU ops to start PMU falcon in low secure mode. -Updated PMU ops update_lspmu_cmdline_args, setup_apertures & secured_pmu_start assignment for gp106 & gv100 to support modified PMU init sequence. -Removed duplicate PMU non-secure bootstrap code from multiple files & defined gm20b_ns_pmu_setup_hw_and_bootstrap()method to handle non secure PMU bootstrap, reused this method for need chips. JIRA NVGPU-1146 Change-Id: I3957da2936b3c4ea0c985e67802c847c38de7c89 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1818099 Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
65 lines
2.7 KiB
C
65 lines
2.7 KiB
C
/*
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* GM20B ACR
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*
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* Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GM20B_ACR_GM20B_H
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#define NVGPU_GM20B_ACR_GM20B_H
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#define GM20B_PMU_UCODE_IMAGE "gpmu_ucode_image.bin"
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#define GM20B_PMU_UCODE_DESC "gpmu_ucode_desc.bin"
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#define GM20B_HSBIN_PMU_UCODE_IMAGE "acr_ucode.bin"
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#define GM20B_HSBIN_PMU_BL_UCODE_IMAGE "pmu_bl.bin"
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#define GM20B_PMU_UCODE_SIG "pmu_sig.bin"
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#define GM20B_FECS_UCODE_SIG "fecs_sig.bin"
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#define T18x_GPCCS_UCODE_SIG "gpccs_sig.bin"
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bool gm20b_is_pmu_supported(struct gk20a *g);
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int prepare_ucode_blob(struct gk20a *g);
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bool gm20b_is_lazy_bootstrap(u32 falcon_id);
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bool gm20b_is_priv_load(u32 falcon_id);
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int gm20b_pmu_populate_loader_cfg(struct gk20a *g,
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void *lsfm, u32 *p_bl_gen_desc_size);
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int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g,
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void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid);
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int acr_ucode_patch_sig(struct gk20a *g,
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unsigned int *p_img,
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unsigned int *p_prod_sig,
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unsigned int *p_dbg_sig,
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unsigned int *p_patch_loc,
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unsigned int *p_patch_ind);
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int gm20b_alloc_blob_space(struct gk20a *g,
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size_t size, struct nvgpu_mem *mem);
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void gm20b_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf);
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int gm20b_acr_patch_wpr_info_to_ucode(struct gk20a *g,
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struct nvgpu_acr *acr, struct hs_acr *acr_desc, bool is_recovery);
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int gm20b_acr_fill_bl_dmem_desc(struct gk20a *g,
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struct nvgpu_acr *acr, struct hs_acr *acr_desc,
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u32 *acr_ucode_header);
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int gm20b_bootstrap_hs_acr(struct gk20a *g, struct nvgpu_acr *acr,
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struct hs_acr *acr_desc);
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void gm20b_remove_acr_support(struct nvgpu_acr *acr);
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void nvgpu_gm20b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr);
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#endif /*NVGPU_GM20B_ACR_GM20B_H*/
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