Files
linux-nvgpu/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
Kirill Artamonov 3b08d73568 gpu: nvgpu: gp10b: add debug features for gfxp and cilp
Add debugfs switch to force cilp and gfx preemption
Add debugfs switch to dump context switch stats on channel
destruction.

bug 1525327
bug 1581799

Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Change-Id: I7d0558cc325ce655411388ea66ad982101f2fe66
Reviewed-on: http://git-master/r/794976
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/677231
2016-12-27 15:22:07 +05:30

59 lines
1.6 KiB
C

/*
* GM20B GPU GR
*
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _NVGPU_GR_GP10B_H_
#define _NVGPU_GR_GP10B_H_
struct gpu_ops;
enum {
PASCAL_CHANNEL_GPFIFO_A = 0xC06F,
PASCAL_A = 0xC097,
PASCAL_COMPUTE_A = 0xC0C0,
PASCAL_DMA_COPY_A = 0xC0B5,
};
#define NVC097_SET_GO_IDLE_TIMEOUT 0x022c
#define NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc
#define NVC097_SET_CIRCULAR_BUFFER_SIZE 0x1280
#define NVC097_SET_SHADER_EXCEPTIONS 0x1528
#define NVC0C0_SET_SHADER_EXCEPTIONS 0x1528
void gp10b_init_gr(struct gpu_ops *ops);
struct gr_t18x {
struct {
u32 preempt_image_size;
u32 force_preemption_gfxp;
u32 force_preemption_cilp;
u32 dump_ctxsw_stats_on_channel_close;
struct dentry *debugfs_force_preemption_cilp;
struct dentry *debugfs_force_preemption_gfxp;
struct dentry *debugfs_dump_ctxsw_stats;
} ctx_vars;
};
struct gr_ctx_desc_t18x {
struct mem_desc preempt_ctxsw_buffer;
struct mem_desc spill_ctxsw_buffer;
struct mem_desc betacb_ctxsw_buffer;
struct mem_desc pagepool_ctxsw_buffer;
};
#define NVGPU_GR_PREEMPTION_MODE_GFXP 1
#define NVGPU_GR_PREEMPTION_MODE_CILP 3
#endif