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A new unit nvgpu_engine_status_info is added. The unit provides a HAL ops function pointer read_engine_status_info() to read and produce a struct of type nvgpu_engine_status_info. Additionally, the unit provides public APIs to retrieve data from the struct nvgpu_engine_status_info. Jira NVGPU-1315 Change-Id: I6c167c36081bee5c9a8db51d3467c8f5f02c2685 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2003886 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
83 lines
3.1 KiB
C
83 lines
3.1 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_ENGINE_STATUS_H
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#define NVGPU_ENGINE_STATUS_H
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#define ENGINE_STATUS_CTX_ID_TYPE_CHID 0U
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#define ENGINE_STATUS_CTX_ID_TYPE_TSGID 1U
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#define ENGINE_STATUS_CTX_ID_TYPE_INVALID (~U32(0U))
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#define ENGINE_STATUS_CTX_NEXT_ID_TYPE_CHID ENGINE_STATUS_CTX_ID_TYPE_CHID
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#define ENGINE_STATUS_CTX_NEXT_ID_TYPE_TSGID ENGINE_STATUS_CTX_ID_TYPE_TSGID
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#define ENGINE_STATUS_CTX_NEXT_ID_TYPE_INVALID ENGINE_STATUS_CTX_ID_TYPE_INVALID
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#define ENGINE_STATUS_CTX_ID_INVALID (~U32(0U))
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#define ENGINE_STATUS_CTX_NEXT_ID_INVALID ENGINE_STATUS_CTX_ID_INVALID
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enum nvgpu_engine_status_ctx_status {
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NVGPU_CTX_STATUS_INVALID,
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NVGPU_CTX_STATUS_VALID,
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NVGPU_CTX_STATUS_CTXSW_LOAD,
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NVGPU_CTX_STATUS_CTXSW_SAVE,
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NVGPU_CTX_STATUS_CTXSW_SWITCH,
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};
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struct nvgpu_engine_status_info {
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u32 reg_data;
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u32 ctx_id;
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u32 ctxsw_state;
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u32 ctx_id_type;
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u32 ctx_next_id;
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u32 ctx_next_id_type;
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bool is_faulted;
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bool is_busy;
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bool ctxsw_in_progress;
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bool in_reload_status;
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enum nvgpu_engine_status_ctx_status ctxsw_status;
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};
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bool nvgpu_engine_status_is_ctxsw_switch(struct nvgpu_engine_status_info
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*engine_status);
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bool nvgpu_engine_status_is_ctxsw_load(struct nvgpu_engine_status_info
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*engine_status);
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bool nvgpu_engine_status_is_ctxsw_save(struct nvgpu_engine_status_info
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*engine_status);
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bool nvgpu_engine_status_is_ctxsw(struct nvgpu_engine_status_info
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*engine_status);
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bool nvgpu_engine_status_is_ctxsw_invalid(struct nvgpu_engine_status_info
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*engine_status);
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bool nvgpu_engine_status_is_ctxsw_valid(struct nvgpu_engine_status_info
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*engine_status);
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bool nvgpu_engine_status_is_ctx_type_tsg(struct nvgpu_engine_status_info
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*engine_status);
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bool nvgpu_engine_status_is_next_ctx_type_tsg(struct nvgpu_engine_status_info
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*engine_status);
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void nvgpu_engine_status_get_ctx_id_type(struct nvgpu_engine_status_info
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*engine_status, u32 *ctx_id, u32 *ctx_type);
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void nvgpu_engine_status_get_next_ctx_id_type(struct nvgpu_engine_status_info
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*engine_status, u32 *ctx_next_id,
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u32 *ctx_next_type);
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#endif /* NVGPU_ENGINE_STATUS_H */
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