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95bfa039f5
Introduce new HAL gops_ltc.set_l2_sector_promotion to configure L2 sector promotion policy. The follow three promotion settings are support: - NVGPU_GPU_IOCTL_TSG_L2_SECTOR_PROMOTE_FLAG_NONE - NVGPU_GPU_IOCTL_TSG_L2_SECTOR_PROMOTE_FLAG_64B - NVGPU_GPU_IOCTL_TSG_L2_SECTOR_PROMOTE_FLAG_128B Add ioctl "NVGPU_TSG_IOCTL_SET_L2_SECTOR_PROMOTION" to the gpu tsg node to support l2 sector promotion. On chips which do not support sector promotion, the ioctl returns 0. Bug 200656177 Change-Id: Iad835a5c954d3b10da436cfafb388aaaa04f44c7 Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2460553 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
49 lines
1.8 KiB
C
49 lines
1.8 KiB
C
/*
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* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef LTC_TU104_H
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#define LTC_TU104_H
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#include <nvgpu/types.h>
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struct gk20a;
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#ifdef CONFIG_NVGPU_DEBUGGER
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/*
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* These macros are based on the TSTG registers present in the refmanual.
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* The first address of register of the TSTG block is:
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* NV_PLTS_TSTG_CFG_0 (0x90) and final register is: NV_PLTS_TSTG_REDUCE_REPLAY
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* (0x114).
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*/
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#define LTS_TSTG_BASE (0x90U)
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#define LTS_TSTG_EXTENT (0x114U)
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#endif
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void ltc_tu104_init_fs_state(struct gk20a *g);
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#ifdef CONFIG_NVGPU_DEBUGGER
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u32 tu104_ltc_pri_is_lts_tstg_addr(struct gk20a *g, u32 addr);
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int tu104_set_l2_sector_promotion(struct gk20a *g, struct nvgpu_tsg *tsg,
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u32 policy);
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#endif
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#endif /* LTC_TU104_H */
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