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25461c7621
Remove the nvlink register read/write code from /common. Move the register handling code to /hal and add HALs to to expose this functionality to common code. JIRA NVGPU-2964 Change-Id: Iafba9f4e29cc0f1130dbf5dd14fbbf8b6b5bb8ec Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2329195 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
96 lines
2.9 KiB
C
96 lines
2.9 KiB
C
/*
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* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifdef CONFIG_NVGPU_NVLINK
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#include <nvgpu/nvgpu_common.h>
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#include <nvgpu/bitops.h>
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#include <nvgpu/nvlink.h>
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#include <nvgpu/enabled.h>
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#include <nvgpu/io.h>
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#include <nvgpu/timers.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/nvlink_minion.h>
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#include "nvlink_gv100.h"
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#include "nvlink_tu104.h"
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#include <nvgpu/hw/tu104/hw_nvl_tu104.h>
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int tu104_nvlink_rxdet(struct gk20a *g, u32 link_id)
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{
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int ret = 0;
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u32 reg;
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struct nvgpu_timeout timeout;
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ret = g->ops.nvlink.minion.send_dlcmd(g, link_id,
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NVGPU_NVLINK_MINION_DLCMD_INITRXTERM, true);
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if (ret != 0) {
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nvgpu_err(g, "Error during INITRXTERM minion DLCMD on link %u",
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link_id);
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return ret;
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}
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ret = g->ops.nvlink.minion.send_dlcmd(g, link_id,
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NVGPU_NVLINK_MINION_DLCMD_TURING_RXDET, true);
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if (ret != 0) {
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nvgpu_err(g, "Error during RXDET minion DLCMD on link %u",
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link_id);
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return ret;
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}
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ret = nvgpu_timeout_init(g, &timeout, NV_NVLINK_REG_POLL_TIMEOUT_MS,
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NVGPU_TIMER_CPU_TIMER);
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if (ret != 0) {
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nvgpu_err(g, "Error during timeout init");
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return ret;
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}
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do {
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reg = DLPL_REG_RD32(g, link_id, nvl_sl0_link_rxdet_status_r());
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if (nvl_sl0_link_rxdet_status_sts_v(reg) ==
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nvl_sl0_link_rxdet_status_sts_found_v()) {
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nvgpu_log(g, gpu_dbg_nvlink,
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"RXDET successful on link %u", link_id);
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return ret;
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}
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if (nvl_sl0_link_rxdet_status_sts_v(reg) ==
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nvl_sl0_link_rxdet_status_sts_timeout_v()) {
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nvgpu_log(g, gpu_dbg_nvlink,
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"RXDET failed on link %u", link_id);
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break;
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}
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nvgpu_udelay(NV_NVLINK_TIMEOUT_DELAY_US);
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} while (nvgpu_timeout_expired_msg(
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&timeout,
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"RXDET status check timed out on link %u",
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link_id) == 0);
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return -ETIMEDOUT;
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}
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void tu104_nvlink_get_connected_link_mask(u32 *link_mask)
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{
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*link_mask = TU104_CONNECTED_LINK_MASK;
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}
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#endif /* CONFIG_NVGPU_NVLINK */
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