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005c9858fb
As part of ACR bootstrap, falcon bootstrap request is sent to engine HAL functions along with bootloader structure & perform falcon boot, but this adds constraint to HAL separation due to struct parameter, so made ACR to handle falcon boot by using falcon interfaces along with new HAL ops to setup engine falcon setup. This also helps to reduce code duplication too. JIRA NVGPU-2039 Change-Id: I6ca29390b74d75bad0467a3c17623a395ec9bc25 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2072940 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
45 lines
2.0 KiB
C
45 lines
2.0 KiB
C
/*
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* GM20B PMU
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*
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* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GM20B_PMU_GM20B_H
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#define NVGPU_GM20B_PMU_GM20B_H
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struct gk20a;
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int gm20b_load_falcon_ucode(struct gk20a *g, u32 falconidmask);
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int gm20b_pmu_setup_elpg(struct gk20a *g);
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void pmu_dump_security_fuses_gm20b(struct gk20a *g);
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void gm20b_pmu_load_lsf(struct gk20a *g, u32 falcon_id, u32 flags);
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int gm20b_pmu_init_acr(struct gk20a *g);
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void gm20b_write_dmatrfbase(struct gk20a *g, u32 addr);
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bool gm20b_pmu_is_debug_mode_en(struct gk20a *g);
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int gm20b_ns_pmu_setup_hw_and_bootstrap(struct gk20a *g);
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void gm20b_pmu_setup_apertures(struct gk20a *g);
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void gm20b_update_lspmu_cmdline_args(struct gk20a *g);
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void gm20b_pmu_flcn_setup_boot_config(struct gk20a *g);
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void gm20b_secured_pmu_start(struct gk20a *g);
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bool gm20b_is_pmu_supported(struct gk20a *g);
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void gm20b_clear_pmu_bar0_host_err_status(struct gk20a *g);
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#endif /*NVGPU_GM20B_PMU_GM20B_H*/
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