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Below sequence leads to the condition where nvgpu logs error about spurious stall intr occurence: 1. PMU interrupt is set after ELPG command is sent to PMU. 2. Stalling irqhandler sees the interrupt and schedules the stalling thread. 3. PMU isr gets executed from nvgpu_pmu_wait_fw_ack_status just before the stalling irq thread is run. Due to this, top level interrupt gets cleared. 4. When stalling irq thread gets executed it sees no interrupt and logs as spurious interrupt. This condition is not actually about "spurious interrupt", hence change error log to gpu_dbg_intr log type and rephrase it. Bug 200780211 Change-Id: Idab62f61007012f7022a836473562795c24821ef Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2628275 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit