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e786c3fc35
-Latest ucode doesn't support get_voltage RPC, the data can be extracted from data obtained by volt_rail_get_status board_obj cmd. Updating the debugfs node to read the data from volt_rail_get_status. JIRA NVGPU-3815 Change-Id: I85f84a757425411725773802c20f05063b222afc Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com> Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2153387 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
117 lines
4.1 KiB
C
117 lines
4.1 KiB
C
/*
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* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_PMU_VOLT_H
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#define NVGPU_PMU_VOLT_H
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#include <nvgpu/types.h>
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#include <nvgpu/boardobjgrp_e32.h>
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struct gk20a;
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#define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES 0x04U
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#define VOLT_GET_VOLT_RAIL(pvolt, rail_idx) \
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((struct voltage_rail *)BOARDOBJGRP_OBJ_GET_BY_IDX( \
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&((pvolt)->volt_rail_metadata.volt_rails.super), (rail_idx)))
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#define VOLT_RAIL_INDEX_IS_VALID(pvolt, rail_idx) \
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(boardobjgrp_idxisvalid( \
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&((pvolt)->volt_rail_metadata.volt_rails.super), (rail_idx)))
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#define VOLT_RAIL_VOLT_3X_SUPPORTED(pvolt) \
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(!BOARDOBJGRP_IS_EMPTY(&((pvolt)->volt_rail_metadata.volt_rails.super)))
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/*!
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* metadata of voltage rail functionality.
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*/
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struct voltage_rail_metadata {
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u8 volt_domain_hal;
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u8 pct_delta;
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u32 ext_rel_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES];
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u8 logic_rail_idx;
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u8 sram_rail_idx;
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struct boardobjgrp_e32 volt_rails;
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};
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struct voltage_device_metadata {
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struct boardobjgrp_e32 volt_devices;
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};
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struct voltage_policy_metadata {
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u8 perf_core_vf_seq_policy_idx;
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struct boardobjgrp_e32 volt_policies;
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};
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struct obj_volt {
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struct voltage_rail_metadata volt_rail_metadata;
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struct voltage_device_metadata volt_dev_metadata;
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struct voltage_policy_metadata volt_policy_metadata;
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};
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struct voltage_rail {
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struct boardobj super;
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u32 boot_voltage_uv;
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u8 rel_limit_vfe_equ_idx;
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u8 alt_rel_limit_vfe_equ_idx;
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u8 ov_limit_vfe_equ_idx;
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u8 pwr_equ_idx;
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u8 volt_scale_exp_pwr_equ_idx;
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u8 volt_dev_idx_default;
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u8 volt_dev_idx_ipc_vmin;
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u8 boot_volt_vfe_equ_idx;
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u8 vmin_limit_vfe_equ_idx;
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u8 volt_margin_limit_vfe_equ_idx;
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u32 volt_margin_limit_vfe_equ_mon_handle;
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u32 rel_limit_vfe_equ_mon_handle;
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u32 alt_rel_limit_vfe_equ_mon_handle;
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u32 ov_limit_vfe_equ_mon_handle;
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struct boardobjgrpmask_e32 volt_dev_mask;
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s32 volt_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES];
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u32 vmin_limitu_v;
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u32 max_limitu_v;
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u32 current_volt_uv;
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};
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int nvgpu_volt_set_voltage(struct gk20a *g, u32 logic_voltage_uv,
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u32 sram_voltage_uv);
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int nvgpu_volt_get_voltage(struct gk20a *g, u32 volt_domain, u32 *voltage_uv);
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int nvgpu_volt_send_load_cmd_to_pmu(struct gk20a *g);
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int nvgpu_volt_dev_sw_setup(struct gk20a *g);
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int nvgpu_volt_dev_pmu_setup(struct gk20a *g);
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int nvgpu_volt_policy_sw_setup(struct gk20a *g);
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int nvgpu_volt_policy_pmu_setup(struct gk20a *g);
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int nvgpu_volt_rail_sw_setup(struct gk20a *g);
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int nvgpu_volt_rail_pmu_setup(struct gk20a *g);
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u8 nvgpu_volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain);
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int nvgpu_volt_get_vmin_vmax_ps35(struct gk20a *g, u32 *vmin_uv, u32 *vmax_uv);
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u8 nvgpu_volt_get_vmargin_ps35(struct gk20a *g);
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int nvgpu_volt_rail_volt_dev_register(struct gk20a *g, struct voltage_rail
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*pvolt_rail, u8 volt_dev_idx, u8 operation_type);
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u8 nvgpu_volt_rail_vbios_volt_domain_convert_to_internal
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(struct gk20a *g, u8 vbios_volt_domain);
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void nvgpu_pmu_volt_rpc_handler(struct gk20a *g, struct nv_pmu_rpc_header *rpc);
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int nvgpu_volt_get_curr_volt_ps35(struct gk20a *g, u32 *vcurr_uv);
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#endif /* NVGPU_PMU_VOLT_H */
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