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e02ea5456b
The ctxsw'ed registers have been moved to a separate list starting from nvgpu_next chip onwards. Hence, update gr_tu104_get_offset_in_gpccs_segment function to account for ctxsw'ed registers in nvgpu_next. Introduce functions: nvgpu_netlist_get_gpc_ctxsw_regs_count to compute the number of ctxsw'ed gpc registers. Bug 2916121 Change-Id: I69fcd8df883af62999d0fa8d1f9a398f8f5d7454 Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2394684 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit