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Rework regops execution API to accomodate below updates for new profiler design - gops.regops.exec_regops() should accept TSG pointer instead of channel pointer. - Remove individual boolean parameters and add one flag field. Below new flags are added to this API : NVGPU_REG_OP_FLAG_MODE_ALL_OR_NONE NVGPU_REG_OP_FLAG_MODE_CONTINUE_ON_ERROR NVGPU_REG_OP_FLAG_ALL_PASSED NVGPU_REG_OP_FLAG_DIRECT_OPS Update other APIs, e.g. gr_gk20a_exec_ctx_ops() and validate_reg_ops() as per new API changes. Add new API gk20a_is_tsg_ctx_resident() to check context residency from TSG pointer. Convert gr_gk20a_ctx_patch_smpc() to a HAL gops.gr.ctx_patch_smpc(). Set this HAL only for gm20b since it is not required for later chips. Also, remove subcontext code from this function since gm20b does not support subcontext. Remove stale comment about missing vGPU support in exec_regops_gk20a() Bug 2510974 Jira NVGPU-5360 Change-Id: I3c25c34277b5ca88484da1e20d459118f15da102 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2389733 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
118 lines
3.3 KiB
C
118 lines
3.3 KiB
C
/*
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* Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/vgpu/vgpu_ivc.h>
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#include <nvgpu/vgpu/tegra_vgpu.h>
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#include <nvgpu/vgpu/vgpu.h>
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#include <nvgpu/debugger.h>
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#include <nvgpu/profiler.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/channel.h>
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#include <nvgpu/string.h>
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#include <nvgpu/regops.h>
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#include "debugger_vgpu.h"
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#include "common/vgpu/ivc/comm_vgpu.h"
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int vgpu_exec_regops(struct gk20a *g,
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struct nvgpu_tsg *tsg,
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struct nvgpu_dbg_reg_op *ops,
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u32 num_ops,
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u32 *flags)
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{
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struct tegra_vgpu_cmd_msg msg;
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struct tegra_vgpu_reg_ops_params *p = &msg.params.reg_ops;
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void *oob;
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size_t oob_size, ops_size;
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void *handle = NULL;
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int err = 0;
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nvgpu_log_fn(g, " ");
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BUG_ON(sizeof(*ops) != sizeof(struct tegra_vgpu_reg_op));
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handle = vgpu_ivc_oob_get_ptr(vgpu_ivc_get_server_vmid(),
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TEGRA_VGPU_QUEUE_CMD,
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&oob, &oob_size);
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if (!handle) {
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return -EINVAL;
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}
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ops_size = sizeof(*ops) * num_ops;
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if (oob_size < ops_size) {
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err = -ENOMEM;
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goto fail;
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}
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nvgpu_memcpy((u8 *)oob, (u8 *)ops, ops_size);
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msg.cmd = TEGRA_VGPU_CMD_REG_OPS;
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msg.handle = vgpu_get_handle(g);
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p->tsg_id = tsg ? tsg->tsgid : U32_MAX;
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p->num_ops = num_ops;
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p->flags = *flags;
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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err = err ? err : msg.ret;
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if (err == 0) {
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nvgpu_memcpy((u8 *)ops, (u8 *)oob, ops_size);
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}
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*flags = p->flags;
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fail:
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vgpu_ivc_oob_put_ptr(handle);
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return err;
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}
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int vgpu_dbg_set_powergate(struct dbg_session_gk20a *dbg_s,
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bool disable_powergate)
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{
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struct tegra_vgpu_cmd_msg msg;
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struct tegra_vgpu_set_powergate_params *p = &msg.params.set_powergate;
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int err = 0;
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u32 mode;
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struct gk20a *g = dbg_s->g;
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nvgpu_log_fn(g, " ");
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/* Just return if requested mode is the same as the session's mode */
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if (disable_powergate) {
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if (dbg_s->is_pg_disabled) {
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return 0;
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}
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dbg_s->is_pg_disabled = true;
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mode = TEGRA_VGPU_POWERGATE_MODE_DISABLE;
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} else {
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if (!dbg_s->is_pg_disabled) {
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return 0;
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}
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dbg_s->is_pg_disabled = false;
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mode = TEGRA_VGPU_POWERGATE_MODE_ENABLE;
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}
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msg.cmd = TEGRA_VGPU_CMD_SET_POWERGATE;
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msg.handle = vgpu_get_handle(dbg_s->g);
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p->mode = mode;
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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err = err ? err : msg.ret;
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return err;
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}
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