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1182a49f5c
For gv11b, priv ring interrupts were not triggered for PLM L2 registers. So, read back was implemented to confirm data written to L2 registers. Verified that LTC registers are not PLM protected, and read back implemented after write is not necessary. Replace nvgpu_writel_check with nvgpu_writel. Bug 200625897 Bug 2989973 Jira NVGPU-5490 Change-Id: Ie0815899589c506e13ab2f9342657cb4d68b8fc8 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2363384 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>