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50dcfe1637
The ecc init, handling for the fb unit is refactored to improve reusability
for nvgpu-next.
The following changes have been done:
- fb.ecc:
This is a new subunit within fb and contains the following functions:
- init: Moved from fb.fb_ecc_init.
- free: Moved from fb.fb_ecc_free.
- l2tlb_error_mask: Fetch bit mask for corrected, uncorrected errors supported
by the unit.
- fb.intr:
This unit has been updated to include the following ecc interrupt, error
handlers:
- handle_ecc: Top level interrupt handler for fb ecc errors.
- handle_ecc_l2tlb: Handle errors within l2tlb memory.
- handle_ecc_hubtlb: Handle errors within hubtlb memory.
- handle_ecc_fillunit: Handle errors within fillunit memory
Jira: NVGPU-5032
Change-Id: I1a26c1823eb992e0e0175250b969f1186dff6e62
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2333271
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
118 lines
3.7 KiB
C
118 lines
3.7 KiB
C
/*
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* GV11B FB
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*
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* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/dma.h>
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#include <nvgpu/log.h>
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#include <nvgpu/enabled.h>
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#include <nvgpu/gmmu.h>
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#include <nvgpu/barrier.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/soc.h>
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#include <nvgpu/ptimer.h>
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#include <nvgpu/io.h>
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#include <nvgpu/utils.h>
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#include <nvgpu/timers.h>
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#include <nvgpu/fifo.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/nvgpu_err.h>
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#include <nvgpu/ltc.h>
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#include <nvgpu/rc.h>
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#include <nvgpu/engines.h>
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#include "fb_gm20b.h"
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#include "fb_gp10b.h"
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#include "fb_gv11b.h"
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#include <nvgpu/hw/gv11b/hw_fb_gv11b.h>
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static void gv11b_init_nvlink_soc_credits(struct gk20a *g)
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{
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#ifndef __NVGPU_POSIX__
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if (nvgpu_is_bpmp_running(g) && (!nvgpu_platform_is_simulation(g))) {
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nvgpu_log(g, gpu_dbg_info, "nvlink soc credits init done by bpmp");
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} else {
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#ifdef CONFIG_NVGPU_NVLINK
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nvgpu_mss_nvlink_init_credits(g);
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#endif
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}
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#endif
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}
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static void gv11b_fb_set_atomic_mode(struct gk20a *g)
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{
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u32 reg_val;
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/*
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* NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE to RMW MODE
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* NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE to L2
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*/
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reg_val = nvgpu_readl(g, fb_mmu_ctrl_r());
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reg_val = set_field(reg_val, fb_mmu_ctrl_atomic_capability_mode_m(),
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fb_mmu_ctrl_atomic_capability_mode_rmw_f());
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reg_val = set_field(reg_val, fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_m(),
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fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_l2_f());
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nvgpu_writel(g, fb_mmu_ctrl_r(), reg_val);
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/* NV_PFB_HSHUB_NUM_ACTIVE_LTCS_HUB_SYS_ATOMIC_MODE to USE_RMW */
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reg_val = nvgpu_readl(g, fb_hshub_num_active_ltcs_r());
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reg_val = set_field(reg_val, fb_hshub_num_active_ltcs_hub_sys_atomic_mode_m(),
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fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f());
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nvgpu_writel(g, fb_hshub_num_active_ltcs_r(), reg_val);
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nvgpu_log(g, gpu_dbg_info, "fb_mmu_ctrl_r 0x%x",
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nvgpu_readl(g, fb_mmu_ctrl_r()));
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nvgpu_log(g, gpu_dbg_info, "fb_hshub_num_active_ltcs_r 0x%x",
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nvgpu_readl(g, fb_hshub_num_active_ltcs_r()));
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}
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void gv11b_fb_init_hw(struct gk20a *g)
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{
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gm20b_fb_init_hw(g);
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g->ops.fb.intr.enable(g);
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}
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void gv11b_fb_init_fs_state(struct gk20a *g)
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{
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nvgpu_log(g, gpu_dbg_fn, "initialize gv11b fb");
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gv11b_init_nvlink_soc_credits(g);
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gv11b_fb_set_atomic_mode(g);
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nvgpu_log(g, gpu_dbg_info, "fbhub active ltcs %x",
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nvgpu_readl(g, fb_fbhub_num_active_ltcs_r()));
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nvgpu_log(g, gpu_dbg_info, "mmu active ltcs %u",
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fb_mmu_num_active_ltcs_count_v(
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nvgpu_readl(g, fb_mmu_num_active_ltcs_r())));
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if (!nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
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/* Bypass MMU check for non-secure boot. For
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* secure-boot,this register write has no-effect */
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nvgpu_writel(g, fb_priv_mmu_phy_secure_r(), U32_MAX);
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}
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}
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