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340ea241cb
Channel debug_dump hal function does not involve any register related code. Move gv11b_channel_debug_dump hal function to common code nvgpu_channel_info_debug_dump function. Check gpu hw version to limit instance variables dump that differs between socs. Add new hal pointer syncpt_debug_dump for pbdma. Jira NVGPU-5109 Signed-off-by: Vinod G <vinodg@nvidia.com> Change-Id: Icfca837ce8e4117387cffa6fadf6c094c7da5946 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2321016 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
47 lines
1.6 KiB
C
47 lines
1.6 KiB
C
/*
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* Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/channel.h>
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#include <nvgpu/log.h>
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#include <nvgpu/atomic.h>
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#include <nvgpu/io.h>
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#include <nvgpu/barrier.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/gk20a.h>
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#include "channel_gk20a.h"
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#include <nvgpu/hw/gk20a/hw_ccsr_gk20a.h>
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void gk20a_channel_unbind(struct nvgpu_channel *ch)
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{
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struct gk20a *g = ch->g;
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nvgpu_log_fn(g, " ");
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if (nvgpu_atomic_cmpxchg(&ch->bound, 1, 0) != 0) {
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gk20a_writel(g, ccsr_channel_inst_r(ch->chid),
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ccsr_channel_inst_ptr_f(0) |
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ccsr_channel_inst_bind_false_f());
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}
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}
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