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Previously, unit interrupt enabling/disabling and corresponding MC level interrupt enabling/disabling was not done at the same time. With this change, stall and nonstall interrupt for units are programmed at MC level along with individual unit interrupts. Kept access to MC interrupt registers through mc.intr_lock spinlock. For doing this separated CE and GR interrupt mask functions. mc.intr_enable is only used when there is global interrupt control to be set. Removed mc_gp10b.c as mc_gp10b_intr_enable is now removed. Removed following functions - mc_gv100_intr_enable, mc_gv11b_intr_enable & intr_tu104_enable. Removed intr_pmu_unit_config as we can use the generic unit interrupt control function. JIRA NVGPU-4336 Change-Id: Ibd296d4a60fda6ba930f18f518ee56ab3f9dacad Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2196178 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
103 lines
3.0 KiB
C
103 lines
3.0 KiB
C
/*
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* GK20A Graphics FIFO (gr host)
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*
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* Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/log.h>
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#include <nvgpu/soc.h>
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#include <nvgpu/io.h>
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#include <nvgpu/fifo.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/power_features/cg.h>
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#include <nvgpu/mc.h>
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#include <nvgpu/gops_mc.h>
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#include "hal/fifo/fifo_gk20a.h"
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#include <nvgpu/hw/gk20a/hw_fifo_gk20a.h>
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static void enable_fifo_interrupts(struct gk20a *g)
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{
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nvgpu_mc_intr_stall_unit_config(g, MC_INTR_UNIT_FIFO, MC_INTR_ENABLE);
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nvgpu_mc_intr_nonstall_unit_config(g, MC_INTR_UNIT_FIFO,
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MC_INTR_ENABLE);
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g->ops.fifo.intr_0_enable(g, true);
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g->ops.fifo.intr_1_enable(g, true);
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}
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int gk20a_init_fifo_reset_enable_hw(struct gk20a *g)
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{
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u32 timeout;
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nvgpu_log_fn(g, " ");
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/* enable pmc pfifo */
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g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_FIFO));
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nvgpu_cg_slcg_fifo_load_enable(g);
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nvgpu_cg_blcg_fifo_load_enable(g);
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timeout = nvgpu_readl(g, fifo_fb_timeout_r());
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timeout = set_field(timeout, fifo_fb_timeout_period_m(),
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fifo_fb_timeout_period_max_f());
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nvgpu_log_info(g, "fifo_fb_timeout reg val = 0x%08x", timeout);
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nvgpu_writel(g, fifo_fb_timeout_r(), timeout);
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g->ops.pbdma.setup_hw(g);
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enable_fifo_interrupts(g);
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nvgpu_log_fn(g, "done");
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return 0;
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}
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int gk20a_init_fifo_setup_hw(struct gk20a *g)
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{
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#ifdef CONFIG_NVGPU_USERD
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struct nvgpu_fifo *f = &g->fifo;
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u64 shifted_addr;
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nvgpu_log_fn(g, " ");
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/* set the base for the userd region now */
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shifted_addr = f->userd_gpu_va >> 12;
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if ((shifted_addr >> 32) != 0U) {
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nvgpu_err(g, "GPU VA > 32 bits %016llx", f->userd_gpu_va);
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return -EFAULT;
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}
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nvgpu_writel(g, fifo_bar1_base_r(),
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fifo_bar1_base_ptr_f(u64_lo32(shifted_addr)) |
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fifo_bar1_base_valid_true_f());
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#endif
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nvgpu_log_fn(g, "done");
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return 0;
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}
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void gk20a_fifo_bar1_snooping_disable(struct gk20a *g)
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{
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nvgpu_writel(g, fifo_bar1_base_r(),
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fifo_bar1_base_valid_false_f());
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}
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