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6ba1f5db3b
Move chip specific functions for teardown_mask_intr and teardown_unmask_intr to hal/fifo/fifo_intr_[chip].[ch] Renamed teardown_mask_intr -> intr_set_recover_mask teardown_unmask_intr -> intr_unset_recover_mask JIRA NVGPU-1314 Change-Id: If233565cbdb09d77cfebd4346edcc3fe64584355 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2093980 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
49 lines
2.0 KiB
C
49 lines
2.0 KiB
C
/*
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* Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_FIFO_INTR_GV11B_H
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#define NVGPU_FIFO_INTR_GV11B_H
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#include <nvgpu/types.h>
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/*
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* ERROR_CODE_BAD_TSG indicates that Host encountered a badly formed TSG header
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* or a badly formed channel type runlist entry in the runlist. This is typically
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* caused by encountering a new TSG entry in the middle of a TSG definition.
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* A channel type entry having wrong runqueue selector can also cause this.
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* Additionally this error code can indicate when a channel is encountered on
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* the runlist which is outside of a TSG.
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*/
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#define SCHED_ERROR_CODE_BAD_TSG 0x00000020U
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struct gk20a;
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void gv11b_fifo_intr_0_enable(struct gk20a *g, bool enable);
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void gv11b_fifo_intr_0_isr(struct gk20a *g);
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bool gv11b_fifo_handle_sched_error(struct gk20a *g);
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void gv11b_fifo_intr_set_recover_mask(struct gk20a *g);
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void gv11b_fifo_intr_unset_recover_mask(struct gk20a *g);
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#endif /* NVGPU_FIFO_INTR_GV11B_H */
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