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a73ca0b70e
Split GR ECC initialization into GPC/TPC and FECS ECC init as FECS ECC errors during acr_construct_execute need to be reported and handled hence FECS ECC counters are required to be initialized before acr_construct_execute. GPC/TPC ECC counters are dependent on the GR config that will be initialized only after acr_construct_execute. nvgpu_gr_intr_init_support is moved to nvgpu_gr_prepare_sw. FECS ECC interrupt is enabled by default hence interrupt is not enabled through gr_fecs_host_int_enable_r in nvgpu_gr_prepare_sw. JIRA NVGPU-4439 Change-Id: Ifc9912f0578015a6ba1e9d38765c42633632b15f Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2261987 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>